From: David S. Miller Date: Tue, 6 Dec 2016 16:32:29 +0000 (-0500) Subject: Merge branch 'mv88e6xxx-rework-reset-and-PPU-code' X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=b1df0f5ceab3cf0207dcb585c51424fe1bb1e1d2;p=linux-beck.git Merge branch 'mv88e6xxx-rework-reset-and-PPU-code' Vivien Didelot says: ==================== net: dsa: mv88e6xxx: rework reset and PPU code Old Marvell chips (like 88E6060) don't have a PHY Polling Unit (PPU). Next chips (like 88E6185) have a PPU, which has exclusive access to the PHY registers, thus must be disabled before access. Newer chips (like 88E6352) have an indirect mechanism to access the PHY registers whenever, thus loose control over the PPU (always enabled). Here's a summary: Model | PPU? | Has PPU ctrl? | PPU state readable? | PHY access ----- | ---- | -------------- | ------------------- | ---------- 6060 | no | no | no | direct 6185 | yes | yes, PPUEn bit | yes, PPUState 2-bit | direct w/ PPU dis. 6352 | yes | no | yes, PPUState 1-bit | indirect 6390 | yes | no | yes, InitState bit | indirect Depending on the PPU control, a switch may have to restart the PPU when resetting the switch. Once the switch is reset, we must wait for the PPU state to be active polling again before accessing the registers. For that purpose, add new operations to the chips to enable/disable the PPU, and execute software reset. With these new ops in place, rework the switch reset code and finally get rid of the MV88E6XXX_FLAG_PPU* flags. Changes in v3: - consider 6097 as 6352 (no PPU ops and use mv88e6352_g1_reset). Changes in v2: - wait in ppu/reset ops so that ppu_polling is not needed anymore. ==================== Signed-off-by: David S. Miller --- b1df0f5ceab3cf0207dcb585c51424fe1bb1e1d2