From: Chanwoo Choi Date: Fri, 2 Dec 2016 06:29:02 +0000 (+0900) Subject: PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 X-Git-Tag: v4.11-rc1~151^2~3^2^2~10 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=b513652443fc515ec90202d005230f2afee457ad;p=karo-tx-linux.git PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 This patch adds the detailed corrleation between sub-blocks and VDD_INT power line for Exynos5433. VDD_INT provided the power source to INT (Internal) block. Signed-off-by: Chanwoo Choi Signed-off-by: MyungJoo Ham --- diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index d3ec8e676b6b..d085ef90d27c 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- FSYS |--- FSYS2 +- In case of Exynos5433, there is VDD_INT power line as following: + VDD_INT |--- G2D (parent device) + |--- MSCL + |--- GSCL + |--- JPEG + |--- MFC + |--- HEVC + |--- BUS0 + |--- BUS1 + |--- BUS2 + |--- PERIS (Fixed clock rate) + |--- PERIC (Fixed clock rate) + |--- FSYS (Fixed clock rate) + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to