From: Rodrigo Vivi Date: Thu, 9 May 2013 17:08:38 +0000 (-0300) Subject: drm/i915: IVB FBC WaFbcDisableDpfcClockGating X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=b74ea102b746a1e5157d6b0c83f486ad3c6235d1;p=linux-beck.git drm/i915: IVB FBC WaFbcDisableDpfcClockGating Display register 42020h bit 9 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: RMW to preserve other bits (by Ville) v3: Fix from Ville: sed &/| at RMW v4: Too far on sed. Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48283167c195..fdc2839448a0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -242,6 +242,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) dpfc_ctl &= ~DPFC_CTL_EN; I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); + if (IS_IVYBRIDGE(dev)) + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) & + ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + DRM_DEBUG_KMS("disabled FBC\n"); } } @@ -270,6 +276,11 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) /* WaFbcAsynchFlipDisableFbcQueue */ I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); + /* WaFbcDisableDpfcClockGating */ + I915_WRITE(ILK_DSPCLK_GATE_D, + I915_READ(ILK_DSPCLK_GATE_D) | + ILK_DPFCUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);