From: Linus Torvalds Date: Fri, 12 Dec 2014 01:56:37 +0000 (-0800) Subject: Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus X-Git-Tag: v3.19-rc1~115 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=c0222ac08666;p=karo-tx-linux.git Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ... --- c0222ac086669a631814bbf857f8c8023452a4d7 diff --cc MAINTAINERS index 34b4b841da40,eedc64bb1865..e186bf90ed8a --- a/MAINTAINERS +++ b/MAINTAINERS @@@ -2110,8 -2115,19 +2124,20 @@@ L: linux-arm-kernel@lists.infradead.or S: Maintained F: arch/arm/mach-bcm/*brcmstb* F: arch/arm/boot/dts/bcm7*.dts* +F: drivers/bus/brcmstb_gisb.c + BROADCOM BMIPS MIPS ARCHITECTURE + M: Kevin Cernekee + M: Florian Fainelli + L: linux-mips@linux-mips.org + S: Maintained + F: arch/mips/bmips/* + F: arch/mips/include/asm/mach-bmips/* + F: arch/mips/kernel/*bmips* + F: arch/mips/boot/dts/bcm*.dts* + F: drivers/irqchip/irq-bcm7* + F: drivers/irqchip/irq-brcmstb* + BROADCOM TG3 GIGABIT ETHERNET DRIVER M: Prashant Sreedharan M: Michael Chan diff --cc arch/mips/Kconfig index 9536ef912f59,0a8e88d06b99..3289969ee423 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@@ -2095,23 -2124,12 +2124,20 @@@ config SB1_PASS_2_1_WORKAROUND default y - config 64BIT_PHYS_ADDR - bool - config ARCH_PHYS_ADDR_T_64BIT - def_bool 64BIT_PHYS_ADDR + bool +choice + prompt "SmartMIPS or microMIPS ASE support" + +config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS + bool "None" + help + Select this if you want neither microMIPS nor SmartMIPS support + config CPU_HAS_SMARTMIPS depends on SYS_SUPPORTS_SMARTMIPS - bool "Support for the SmartMIPS ASE" + bool "SmartMIPS" help SmartMIPS is a extension of the MIPS32 architecture aimed at increased security at both hardware and software level for @@@ -2122,8 -2140,8 +2148,8 @@@ here. config CPU_MICROMIPS - depends on SYS_SUPPORTS_MICROMIPS + depends on 32BIT && SYS_SUPPORTS_MICROMIPS - bool "Build kernel using microMIPS ISA" + bool "microMIPS" help When this option is enabled the kernel will be built using the microMIPS ISA diff --cc drivers/clocksource/Makefile index fae0435cc23d,e23fc2d5fc27..94d90b24b56b --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@@ -45,5 -45,5 +45,6 @@@ obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_ obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o +obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o + obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o diff --cc drivers/irqchip/Makefile index f0909d05eae3,021833079c91..4954a314c31e --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@@ -35,6 -35,7 +35,7 @@@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x. obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o -obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \ - irq-bcm7120-l2.o +obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o +obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o + obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o