From: Daniel Vetter Date: Fri, 13 Apr 2012 13:51:51 +0000 (+0200) Subject: drm/i915: don't pwrite tiled objects through the gtt X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=c07496fa61f4c5cb2addd1c57f6b22fcaeea2eeb;p=linux-beck.git drm/i915: don't pwrite tiled objects through the gtt ... we will botch up the bit17 swizzling. Furthermore tiled pwrite is a (now) unused slowpath, so no one really cares. This fixes the last swizzling issues I have with i-g-t on my bit17 swizzling i915G. No regression, it's been broken since the dawn of gem, but it's nice for regression tracking when really _all_ i-g-t tests work. Actually this is not true, Chris Wilson noticed while reviewing this patch that the commit commit d9e86c0ee60f323e890484628f351bf50fa9a15d Author: Chris Wilson Date: Wed Nov 10 16:40:20 2010 +0000 drm/i915: Pipelined fencing [infrastructure] contained a functional change that broke things. Reviewed-by: Chris Wilson Signed-Off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 71934dd0ee43..9415c07b6285 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -876,6 +876,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, if (obj->gtt_space && obj->cache_level == I915_CACHE_NONE && + obj->tiling_mode == I915_TILING_NONE && obj->map_and_fenceable && obj->base.write_domain != I915_GEM_DOMAIN_CPU) { ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);