From: Ian Abbott Date: Tue, 5 May 2015 17:47:27 +0000 (+0100) Subject: staging: comedi: gsc_hpdi: prefer using the BIT() macro X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=c5f2579ed3eae33d41299958af6af56c0c8a01ba;p=linux-beck.git staging: comedi: gsc_hpdi: prefer using the BIT() macro Fix all the checkpatch issues "CHECK: Prefer using the BIT macro". Signed-off-by: Ian Abbott Reviewed-by: H Hartley Sweeten Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c index 31ff10807260..2e459f6d6fe0 100644 --- a/drivers/staging/comedi/drivers/gsc_hpdi.c +++ b/drivers/staging/comedi/drivers/gsc_hpdi.c @@ -52,45 +52,45 @@ * PCI BAR2 Register map (dev->mmio) */ #define FIRMWARE_REV_REG 0x00 -#define FEATURES_REG_PRESENT_BIT (1 << 15) +#define FEATURES_REG_PRESENT_BIT BIT(15) #define BOARD_CONTROL_REG 0x04 -#define BOARD_RESET_BIT (1 << 0) -#define TX_FIFO_RESET_BIT (1 << 1) -#define RX_FIFO_RESET_BIT (1 << 2) -#define TX_ENABLE_BIT (1 << 4) -#define RX_ENABLE_BIT (1 << 5) -#define DEMAND_DMA_DIRECTION_TX_BIT (1 << 6) /* ch 0 only */ -#define LINE_VALID_ON_STATUS_VALID_BIT (1 << 7) -#define START_TX_BIT (1 << 8) -#define CABLE_THROTTLE_ENABLE_BIT (1 << 9) -#define TEST_MODE_ENABLE_BIT (1 << 31) +#define BOARD_RESET_BIT BIT(0) +#define TX_FIFO_RESET_BIT BIT(1) +#define RX_FIFO_RESET_BIT BIT(2) +#define TX_ENABLE_BIT BIT(4) +#define RX_ENABLE_BIT BIT(5) +#define DEMAND_DMA_DIRECTION_TX_BIT BIT(6) /* ch 0 only */ +#define LINE_VALID_ON_STATUS_VALID_BIT BIT(7) +#define START_TX_BIT BIT(8) +#define CABLE_THROTTLE_ENABLE_BIT BIT(9) +#define TEST_MODE_ENABLE_BIT BIT(31) #define BOARD_STATUS_REG 0x08 #define COMMAND_LINE_STATUS_MASK (0x7f << 0) -#define TX_IN_PROGRESS_BIT (1 << 7) -#define TX_NOT_EMPTY_BIT (1 << 8) -#define TX_NOT_ALMOST_EMPTY_BIT (1 << 9) -#define TX_NOT_ALMOST_FULL_BIT (1 << 10) -#define TX_NOT_FULL_BIT (1 << 11) -#define RX_NOT_EMPTY_BIT (1 << 12) -#define RX_NOT_ALMOST_EMPTY_BIT (1 << 13) -#define RX_NOT_ALMOST_FULL_BIT (1 << 14) -#define RX_NOT_FULL_BIT (1 << 15) -#define BOARD_JUMPER0_INSTALLED_BIT (1 << 16) -#define BOARD_JUMPER1_INSTALLED_BIT (1 << 17) -#define TX_OVERRUN_BIT (1 << 21) -#define RX_UNDERRUN_BIT (1 << 22) -#define RX_OVERRUN_BIT (1 << 23) +#define TX_IN_PROGRESS_BIT BIT(7) +#define TX_NOT_EMPTY_BIT BIT(8) +#define TX_NOT_ALMOST_EMPTY_BIT BIT(9) +#define TX_NOT_ALMOST_FULL_BIT BIT(10) +#define TX_NOT_FULL_BIT BIT(11) +#define RX_NOT_EMPTY_BIT BIT(12) +#define RX_NOT_ALMOST_EMPTY_BIT BIT(13) +#define RX_NOT_ALMOST_FULL_BIT BIT(14) +#define RX_NOT_FULL_BIT BIT(15) +#define BOARD_JUMPER0_INSTALLED_BIT BIT(16) +#define BOARD_JUMPER1_INSTALLED_BIT BIT(17) +#define TX_OVERRUN_BIT BIT(21) +#define RX_UNDERRUN_BIT BIT(22) +#define RX_OVERRUN_BIT BIT(23) #define TX_PROG_ALMOST_REG 0x0c #define RX_PROG_ALMOST_REG 0x10 #define ALMOST_EMPTY_BITS(x) (((x) & 0xffff) << 0) #define ALMOST_FULL_BITS(x) (((x) & 0xff) << 16) #define FEATURES_REG 0x14 -#define FIFO_SIZE_PRESENT_BIT (1 << 0) -#define FIFO_WORDS_PRESENT_BIT (1 << 1) -#define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT (1 << 2) -#define GPIO_SUPPORTED_BIT (1 << 3) -#define PLX_DMA_CH1_SUPPORTED_BIT (1 << 4) -#define OVERRUN_UNDERRUN_SUPPORTED_BIT (1 << 5) +#define FIFO_SIZE_PRESENT_BIT BIT(0) +#define FIFO_WORDS_PRESENT_BIT BIT(1) +#define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT BIT(2) +#define GPIO_SUPPORTED_BIT BIT(3) +#define PLX_DMA_CH1_SUPPORTED_BIT BIT(4) +#define OVERRUN_UNDERRUN_SUPPORTED_BIT BIT(5) #define FIFO_REG 0x18 #define TX_STATUS_COUNT_REG 0x1c #define TX_LINE_VALID_COUNT_REG 0x20, @@ -98,16 +98,16 @@ #define RX_STATUS_COUNT_REG 0x28 #define RX_LINE_COUNT_REG 0x2c #define INTERRUPT_CONTROL_REG 0x30 -#define FRAME_VALID_START_INTR (1 << 0) -#define FRAME_VALID_END_INTR (1 << 1) -#define TX_FIFO_EMPTY_INTR (1 << 8) -#define TX_FIFO_ALMOST_EMPTY_INTR (1 << 9) -#define TX_FIFO_ALMOST_FULL_INTR (1 << 10) -#define TX_FIFO_FULL_INTR (1 << 11) -#define RX_EMPTY_INTR (1 << 12) -#define RX_ALMOST_EMPTY_INTR (1 << 13) -#define RX_ALMOST_FULL_INTR (1 << 14) -#define RX_FULL_INTR (1 << 15) +#define FRAME_VALID_START_INTR BIT(0) +#define FRAME_VALID_END_INTR BIT(1) +#define TX_FIFO_EMPTY_INTR BIT(8) +#define TX_FIFO_ALMOST_EMPTY_INTR BIT(9) +#define TX_FIFO_ALMOST_FULL_INTR BIT(10) +#define TX_FIFO_FULL_INTR BIT(11) +#define RX_EMPTY_INTR BIT(12) +#define RX_ALMOST_EMPTY_INTR BIT(13) +#define RX_ALMOST_FULL_INTR BIT(14) +#define RX_FULL_INTR BIT(15) #define INTERRUPT_STATUS_REG 0x34 #define TX_CLOCK_DIVIDER_REG 0x38 #define TX_FIFO_SIZE_REG 0x40