From: Yakir Yang Date: Wed, 29 Jun 2016 09:15:05 +0000 (+0800) Subject: drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=cb5571fcf809860c455f6b62bb5252f277b52e83;p=linux-beck.git drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special registers setting"). The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 BIT 0, not BIT 1. Signed-off-by: Yakir Yang Reviewed-by: Sean Paul Reviewed-by: Tomasz Figa Tested-by: Javier Martinez Canillas --- diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 337912b0aeab..88d56ad5c010 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -163,8 +163,8 @@ #define HSYNC_POLARITY_CFG (0x1 << 0) /* ANALOGIX_DP_PLL_REG_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)