From: Arnd Bergmann <arnd@arndb.de>
Date: Fri, 2 Mar 2012 15:04:47 +0000 (+0000)
Subject: Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=cb66bb1d6fab2d91960c20f256c6986d5afac1a1;p=linux-beck.git

Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc

* 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: mx3: Setup AIPS registers
  ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI

Conflicts:
	arch/arm/mach-imx/mm-imx3.c
---

cb66bb1d6fab2d91960c20f256c6986d5afac1a1
diff --cc arch/arm/mach-imx/mm-imx3.c
index 8404ee72555a,35ce8b5fe75d..b23bd3f09a60
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -34,29 -34,33 +34,31 @@@ static void imx3_idle(void
  {
  	unsigned long reg = 0;
  
+ 	mx3_cpu_lp_set(MX3_WAIT);
+ 
 -	if (!need_resched())
 -		__asm__ __volatile__(
 -			/* disable I and D cache */
 -			"mrc p15, 0, %0, c1, c0, 0\n"
 -			"bic %0, %0, #0x00001000\n"
 -			"bic %0, %0, #0x00000004\n"
 -			"mcr p15, 0, %0, c1, c0, 0\n"
 -			/* invalidate I cache */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c5, 0\n"
 -			/* clear and invalidate D cache */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c14, 0\n"
 -			/* WFI */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c0, 4\n"
 -			"nop\n" "nop\n" "nop\n" "nop\n"
 -			"nop\n" "nop\n" "nop\n"
 -			/* enable I and D cache */
 -			"mrc p15, 0, %0, c1, c0, 0\n"
 -			"orr %0, %0, #0x00001000\n"
 -			"orr %0, %0, #0x00000004\n"
 -			"mcr p15, 0, %0, c1, c0, 0\n"
 -			: "=r" (reg));
 -	local_irq_enable();
 +	__asm__ __volatile__(
 +		/* disable I and D cache */
 +		"mrc p15, 0, %0, c1, c0, 0\n"
 +		"bic %0, %0, #0x00001000\n"
 +		"bic %0, %0, #0x00000004\n"
 +		"mcr p15, 0, %0, c1, c0, 0\n"
 +		/* invalidate I cache */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c5, 0\n"
 +		/* clear and invalidate D cache */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c14, 0\n"
 +		/* WFI */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c0, 4\n"
 +		"nop\n" "nop\n" "nop\n" "nop\n"
 +		"nop\n" "nop\n" "nop\n"
 +		/* enable I and D cache */
 +		"mrc p15, 0, %0, c1, c0, 0\n"
 +		"orr %0, %0, #0x00001000\n"
 +		"orr %0, %0, #0x00000004\n"
 +		"mcr p15, 0, %0, c1, c0, 0\n"
 +		: "=r" (reg));
  }
  
  static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,