From: Zhenyu Wang Date: Tue, 2 Nov 2010 09:30:46 +0000 (+0800) Subject: agp/intel: fix cache control for sandybridge X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=d110852513148a7ec44fad4e036455aeb816d713;p=mv-sheeva.git agp/intel: fix cache control for sandybridge This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang Signed-off-by: Chris Wilson --- diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index f800e9cfc36..c51efe6f2c7 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1291,11 +1291,11 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, if (type_mask == AGP_USER_UNCACHED_MEMORY) pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { - pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; } else { /* set 'normal'/'cached' to LLC by default */ - pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; }