From: Daniel Vetter Date: Wed, 21 May 2014 09:45:40 +0000 (+0200) Subject: Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queued X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=d40d91876a58979374e39722399ee93e870a44c9;p=linux-beck.git Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queued Pull in the drm vblank rework from Ville and me. drm core parts acked by Dave Airlie Conflicts: drivers/gpu/drm/i915/intel_display.c Just a bit of fun around the placement of drm_vblank_on. This merge resolution has been tested in drm-intel-nightly for a while already. Acked-by: Dave Airlie Signed-off-by: Daniel Vetter --- d40d91876a58979374e39722399ee93e870a44c9 diff --cc drivers/gpu/drm/i915/intel_display.c index 7def8261eaac,83fe9be03f5c..5f803f436872 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@@ -3998,8 -3726,19 +3998,9 @@@ static void ironlake_crtc_enable(struc if (HAS_PCH_CPT(dev)) cpt_verify_modeset(dev, intel_crtc->pipe); - ilk_crtc_enable_planes(crtc); - - /* - * There seems to be a race in PCH platform hw (at least on some - * outputs) where an enabled pipe still completes any pageflip right - * away (as if the pipe is off) instead of waiting for vblank. As soon - * as the first vblank happend, everything works as expected. Hence just - * wait for one vblank before returning to avoid strange things - * happening. - */ - intel_wait_for_vblank(dev, intel_crtc->pipe); + intel_crtc_enable_planes(crtc); + drm_crtc_vblank_on(crtc); } /* IPS only exists on ULT machines and is tied to pipe A. */ @@@ -4112,7 -3829,9 +4113,9 @@@ static void haswell_crtc_enable(struct /* If we change the relative order between pipe/planes enabling, we need * to change the workaround. */ haswell_mode_set_planes_workaround(intel_crtc); - ilk_crtc_enable_planes(crtc); + intel_crtc_enable_planes(crtc); + + drm_crtc_vblank_on(crtc); } static void ironlake_pfit_disable(struct intel_crtc *crtc) @@@ -4619,18 -4350,15 +4622,20 @@@ static void valleyview_crtc_enable(stru for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); + intel_crtc_enable_planes(crtc); ++ + drm_crtc_vblank_on(crtc); } +static void i9xx_set_pll_dividers(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); + I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); +} + static void i9xx_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@@ -4696,7 -4393,19 +4701,9 @@@ for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); + intel_crtc_enable_planes(crtc); ++ + drm_crtc_vblank_on(crtc); } static void i9xx_pfit_disable(struct intel_crtc *crtc)