From: Kishon Vijay Abraham I <kishon@ti.com>
Date: Mon, 23 Feb 2015 13:09:45 +0000 (+0530)
Subject: ARM: AM43xx: Enable clocks for USB OTGSS and USB PHY
X-Git-Tag: KARO-TX6-2015-09-18~2891
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=d42bd109d0d3bb45c94aae3d626f9f0c5049a8cc;p=karo-tx-uboot.git

ARM: AM43xx: Enable clocks for USB OTGSS and USB PHY

Enabled clocks for dwc3 controller and USB PHY present in AM43xx.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
---

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 529a119514..b1c0025eeb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -111,9 +111,21 @@ void enable_basic_clocks(void)
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
 		&cmper->qspiclkctrl,
+		&cmper->usb0clkctrl,
+		&cmper->usbphyocp2scp0clkctrl,
+		&cmper->usb1clkctrl,
+		&cmper->usbphyocp2scp1clkctrl,
 		0
 	};
 
+	setbits_le32(&cmper->usb0clkctrl,
+		     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+	setbits_le32(&cmwkup->usbphy0clkctrl,
+		     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	setbits_le32(&cmper->usb1clkctrl,
+		     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+	setbits_le32(&cmwkup->usbphy1clkctrl,
+		     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
 	/* Select the Master osc clk as Timer2 clock source */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 56e84a9c97..e34f71cfc2 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -232,7 +232,11 @@ struct prm_device_inst {
 struct cm_wkuppll {
 	unsigned int resv0[136];
 	unsigned int wkl4wkclkctrl;	/* offset 0x220 */
-	unsigned int resv1[55];
+	unsigned int resv1[7];
+	unsigned int usbphy0clkctrl;	/* offset 0x240 */
+	unsigned int resv112;
+	unsigned int usbphy1clkctrl;	/* offset 0x248 */
+	unsigned int resv113[45];
 	unsigned int wkclkstctrl;	/* offset 0x300 */
 	unsigned int resv2[15];
 	unsigned int wkup_i2c0ctrl;	/* offset 0x340 */
@@ -291,7 +295,7 @@ struct cm_perpll {
 	unsigned int l3clkstctrl;	/* offset 0x00 */
 	unsigned int resv0[7];
 	unsigned int l3clkctrl;		/* Offset 0x20 */
-	unsigned int resv1[7];
+	unsigned int resv112[7];
 	unsigned int l3instrclkctrl;	/* offset 0x40 */
 	unsigned int resv2[3];
 	unsigned int ocmcramclkctrl;	/* offset 0x50 */
@@ -318,7 +322,9 @@ struct cm_perpll {
 	unsigned int qspiclkctrl;       /* offset 0x258 */
 	unsigned int resv121;
 	unsigned int usb0clkctrl;	/* offset 0x260 */
-	unsigned int resv13[103];
+	unsigned int resv122;
+	unsigned int usb1clkctrl;	/* offset 0x268 */
+	unsigned int resv13[101];
 	unsigned int l4lsclkstctrl;	/* offset 0x400 */
 	unsigned int resv14[7];
 	unsigned int l4lsclkctrl;	/* offset 0x420 */
@@ -372,10 +378,14 @@ struct cm_perpll {
 	unsigned int uart4clkctrl;	/* offset 0x598 */
 	unsigned int resv35;
 	unsigned int uart5clkctrl;	/* offset 0x5A0 */
-	unsigned int resv36[87];
+	unsigned int resv36[5];
+	unsigned int usbphyocp2scp0clkctrl;	/* offset 0x5B8 */
+	unsigned int resv361;
+	unsigned int usbphyocp2scp1clkctrl;	/* offset 0x5C0 */
+	unsigned int resv3611[79];
 
 	unsigned int emifclkstctrl;	/* offset 0x700 */
-	unsigned int resv361[7];
+	unsigned int resv362[7];
 	unsigned int emifclkctrl;	/* offset 0x720 */
 	unsigned int resv37[3];
 	unsigned int emiffwclkctrl;	/* offset 0x730 */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 29e3816c1a..f6523ea927 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -73,6 +73,9 @@
 #define CM_DEVICE_INST			0x44df4100
 #define PRM_DEVICE_INST			0x44df4000
 
+#define	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960	(1 << 8)
+#define	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
 /* Control status register */
 #define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31