From: Kim Phillips Date: Tue, 20 Nov 2007 01:04:43 +0000 (-0600) Subject: [POWERPC] 83xx: mpc832x mds: Fix board PHY reset code X-Git-Tag: v2.6.24-rc4~109^2~5^2~4 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=d8ecbb93bece05df84e654c296c3c81b3d347c2d;p=karo-tx-linux.git [POWERPC] 83xx: mpc832x mds: Fix board PHY reset code currently the board-level PHY reset code for the mpc832x MDS messes with reset configuration words source settings which is plain wrong (it looks like this board code was cut-n-pasted from the mpc8360 mds code, which has the PHY reset bits in a different BCSR); this patch points the PHY reset code to the proper mpc832x mds PHY reset bits in the BCSR. Signed-off-by: Peter Van Ackeren Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index 972fa8528a8c..9e3bfcca1cea 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ - /* Reset the Ethernet PHY */ - bcsr_regs[9] &= ~0x20; + /* Reset the Ethernet PHYs */ +#define BCSR8_FETH_RST 0x50 + bcsr_regs[8] &= ~BCSR8_FETH_RST; udelay(1000); - bcsr_regs[9] |= 0x20; + bcsr_regs[8] |= BCSR8_FETH_RST; iounmap(bcsr_regs); of_node_put(np); }