From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Wed, 25 Jul 2012 00:43:28 +0000 (+1000)
Subject: Merge remote-tracking branch 'drm/drm-next'
X-Git-Tag: next-20120725~55
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=d97e22786074ca7f28c74a7462c1cb4782777bd2;p=karo-tx-linux.git

Merge remote-tracking branch 'drm/drm-next'

Conflicts:
	include/linux/pci_regs.h
---

d97e22786074ca7f28c74a7462c1cb4782777bd2
diff --cc include/linux/pci_regs.h
index 53274bff5773,7f04132eb02d..7fb75b143755
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@@ -542,7 -521,11 +542,12 @@@
  #define  PCI_EXP_OBFF_MSGA_EN	0x2000	/* OBFF enable with Message type A */
  #define  PCI_EXP_OBFF_MSGB_EN	0x4000	/* OBFF enable with Message type B */
  #define  PCI_EXP_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */
 +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	44	/* v2 endpoints end here */
+ #define PCI_EXP_LNKCAP2		44	/* Link Capability 2 */
+ #define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x01	/* Current Link Speed 2.5GT/s */
+ #define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x02	/* Current Link Speed 5.0GT/s */
+ #define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04	/* Current Link Speed 8.0GT/s */
+ #define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
  #define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
  #define PCI_EXP_SLTCTL2		56	/* Slot Control 2 */