From: Anson Huang <b20788@freescale.com>
Date: Fri, 28 Sep 2012 18:42:52 +0000 (-0400)
Subject: ENGR00227245 mx6q: Remove 400M setpoint for bus freq
X-Git-Tag: v3.0.35-fsl~393
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=deb3b5f36778ed41b4198b9c17fb21e5117f29fc;p=karo-tx-linux.git

ENGR00227245 mx6q: Remove 400M setpoint for bus freq

Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.

Signed-off-by: Anson Huang <b20788@freescale.com>
---

diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index 9d18423c85c5..d96ac6a1e928 100644
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -412,7 +412,7 @@ void bus_freq_update(struct clk *clk, bool flag)
 			  */
 			high_cpu_freq = 1;
 			if (low_bus_freq_mode || audio_bus_freq_mode)
-				set_high_bus_freq(0);
+				set_high_bus_freq(1);
 		} else {
 			/* Update count */
 			if (clk->flags & AHB_HIGH_SET_POINT)
@@ -471,7 +471,7 @@ void bus_freq_update(struct clk *clk, bool flag)
 					/* Set to either high or
 					  * medium setpoint.
 					  */
-					set_high_bus_freq(0);
+					set_high_bus_freq(1);
 				}
 			}
 		}
@@ -506,7 +506,7 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
 #else
 		bus_freq_scaling_is_active = 1;
 #endif
-		set_high_bus_freq(0);
+		set_high_bus_freq(1);
 		/* Make sure system can enter low bus mode if it should be in
 		low bus mode */
 		if (low_freq_bus_used() && !low_bus_freq_mode)
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 6bf6ef7e29ac..67c3d1fa6fd1 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -4853,7 +4853,7 @@ static struct clk usboh3_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
 	.disable = _clk_disable,
 	.secondary = &usboh3_clk[1],
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	},
 	{
 	.parent = &mmdc_ch0_axi_clk[0],