From: Michael Turquette <mturquette@baylibre.com>
Date: Tue, 22 Dec 2015 18:12:42 +0000 (-0800)
Subject: Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=eaaa6fb53f2652760c1c512534fe3e71672a7d78;p=linux-beck.git

Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
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eaaa6fb53f2652760c1c512534fe3e71672a7d78