From: Huang Shijie Date: Mon, 30 Aug 2010 01:51:18 +0000 (+0800) Subject: ENGR00141399-5 OCOTP: add the ocotp driver X-Git-Tag: v3.0.35-fsl_4.1.0~2618 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=eb945d2cc25b933ef6628e96fc005adecf26d687;p=karo-tx-linux.git ENGR00141399-5 OCOTP: add the ocotp driver Add a new driver for On-Chip OTP controller. The driver will register all the register names of all the banks to /sys/. You can use the following commands to manipulate the OTP banks: read: #cat HW_OCOTP_MAC0 write: #echo 0x11223344 > HW_OCOTP_MAC0 Signed-off-by: Huang Shijie --- diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index bdefe0936237..b9c85171b4ea 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -109,6 +109,22 @@ config BFIN_OTP_WRITE_ENABLE If unsure, say N. +config FSL_OTP + tristate "Freescale On-Chip OTP Memory Support" + depends on (ARCH_MX23 || ARCH_MX28 || ARCH_MX50) + default n + help + If you say Y here, you will get support for a character device + interface into the One Time Programmable memory pages that are + stored on the iMX23/28/50 processor. This will not get you access + to the secure memory pages however. You will need to write your + own secure code and reader for that. + + To compile this driver as a module, choose M here: the module + will be called fsl_otp. + + If unsure, it is safe to say Y. + config PRINTER tristate "Parallel printer support" depends on PARPORT diff --git a/drivers/char/Makefile b/drivers/char/Makefile index caaf67a94c57..0103fecd7927 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_IBM_BSR) += bsr.o obj-$(CONFIG_SGI_MBCS) += mbcs.o obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o obj-$(CONFIG_BFIN_OTP) += bfin-otp.o +obj-$(CONFIG_FSL_OTP) += fsl_otp.o obj-$(CONFIG_PRINTER) += lp.o diff --git a/drivers/char/fsl_otp.c b/drivers/char/fsl_otp.c new file mode 100755 index 000000000000..d083036929f8 --- /dev/null +++ b/drivers/char/fsl_otp.c @@ -0,0 +1,241 @@ +/* + * Freescale On-Chip OTP driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsl_otp.h" + +static DEFINE_MUTEX(otp_mutex); +static struct kobject *otp_kobj; +static struct attribute **attrs; +static struct kobj_attribute *kattr; +static struct attribute_group attr_group; +static struct mxc_otp_platform_data *otp_data; + +static inline unsigned int get_reg_index(struct kobj_attribute *tmp) +{ + return tmp - kattr; +} + +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + if (count < 0) + return -ETIMEDOUT; + return 0; +} + +static ssize_t otp_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + unsigned int index = get_reg_index(attr); + u32 value = 0; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + mutex_lock(&otp_mutex); + + if (otp_read_prepare()) { + mutex_unlock(&otp_mutex); + return 0; + } + value = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(index)); + otp_read_post(); + + mutex_unlock(&otp_mutex); + return sprintf(buf, "0x%x\n", value); +} + +static int otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(addr, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL); + + /* init the data register */ + __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + return 0; +} + +static ssize_t otp_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int index = get_reg_index(attr); + int value; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + sscanf(buf, "0x%x", &value); + + mutex_lock(&otp_mutex); + if (otp_write_prepare(otp_data)) { + mutex_unlock(&otp_mutex); + return 0; + } + otp_write_bits(index, value, 0x3e77); + otp_write_post(); + mutex_unlock(&otp_mutex); + return count; +} + +static void free_otp_attr(void) +{ + kfree(attrs); + attrs = NULL; + + kfree(kattr); + kattr = NULL; +} + +static int __init alloc_otp_attr(struct mxc_otp_platform_data *pdata) +{ + int i; + + otp_data = pdata; /* get private data */ + + /* The last one is NULL, which is used to detect the end */ + attrs = kzalloc((otp_data->fuse_num + 1) * sizeof(attrs[0]), + GFP_KERNEL); + kattr = kzalloc(otp_data->fuse_num * sizeof(struct kobj_attribute), + GFP_KERNEL); + + if (!attrs || !kattr) + goto error_out; + + for (i = 0; i < otp_data->fuse_num; i++) { + kattr[i].attr.name = pdata->fuse_name[i]; + kattr[i].attr.mode = 0600; + kattr[i].show = otp_show; + kattr[i].store = otp_store; + + attrs[i] = &kattr[i].attr; + } + memset(&attr_group, 0, sizeof(attr_group)); + attr_group.attrs = attrs; + return 0; + +error_out: + free_otp_attr(); + return -ENOMEM; +} + +static int __devinit fsl_otp_probe(struct platform_device *pdev) +{ + int retval; + struct mxc_otp_platform_data *pdata; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) + return -ENODEV; + + retval = alloc_otp_attr(pdata); + if (retval) + return retval; + + retval = map_ocotp_addr(pdev); + if (retval) + goto error; + + otp_kobj = kobject_create_and_add("fsl_otp", NULL); + if (!otp_kobj) { + retval = -ENOMEM; + goto error; + } + + retval = sysfs_create_group(otp_kobj, &attr_group); + if (retval) + goto error; + + mutex_init(&otp_mutex); + return 0; +error: + kobject_put(otp_kobj); + otp_kobj = NULL; + free_otp_attr(); + unmap_ocotp_addr(); + return retval; +} + +static int otp_remove(struct platform_device *pdev) +{ + kobject_put(otp_kobj); + otp_kobj = NULL; + + free_otp_attr(); + unmap_ocotp_addr(); + return 0; +} + +static struct platform_driver ocotp_driver = { + .probe = fsl_otp_probe, + .remove = otp_remove, + .driver = { + .name = "imx-ocotp", + .owner = THIS_MODULE, + }, +}; + +static int __init fsl_otp_init(void) +{ + return platform_driver_register(&ocotp_driver); +} + +static void __exit fsl_otp_exit(void) +{ + platform_driver_unregister(&ocotp_driver); +} +module_init(fsl_otp_init); +module_exit(fsl_otp_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huang Shijie "); +MODULE_DESCRIPTION("Common driver for OTP controller"); diff --git a/drivers/char/fsl_otp.h b/drivers/char/fsl_otp.h new file mode 100755 index 000000000000..f1124892d465 --- /dev/null +++ b/drivers/char/fsl_otp.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __FREESCALE_OTP__ +#define __FREESCALE_OTP__ + +#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \ + __func__, __LINE__, ## __VA_ARGS__) + +static int otp_wait_busy(u32 flags); + +/* IMX23 and IMX28 share most of the defination ========================= */ +#if (defined(CONFIG_ARCH_MX23) || defined(CONFIG_ARCH_MX28)) + +#include +#include +#include +#include +#include + +#if defined(CONFIG_ARCH_MX23) +#include +#else +#include +#endif + +#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR)) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +static unsigned long otp_hclk_saved; +static u32 otp_voltage_saved; +struct regulator *regu; + +/* open the bank for the imx23/imx28 */ +static int otp_read_prepare(void) +{ + int r; + + /* [1] set the HCLK */ + /* [2] check BUSY and ERROR bit */ + r = otp_wait_busy(0); + if (r < 0) + goto error; + + /* [3] open bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(10); + + /* [4] wait for BUSY */ + r = otp_wait_busy(0); + return 0; +error: + return r; +} + +static int otp_read_post(void) +{ + /* [5] close bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR); + return 0; +} + +static int otp_write_prepare(struct fsl_otp_data *otp_data) +{ + struct clk *hclk; + int err = 0; + + /* [1] HCLK to 24MHz. */ + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + err = PTR_ERR(hclk); + goto out; + } + /* + WARNING ACHTUNG UWAGA + + the code below changes HCLK clock rate to 24M. This is + required to write OTP bits (7.2.2 in STMP378x Target + Specification), and might affect LCD operation, for example. + Moreover, this hacky code changes VDDIO to 2.8V; and resto- + res it only on otp_close(). This may affect... anything. + + You are warned now. + */ + otp_hclk_saved = clk_get_rate(hclk); + clk_set_rate(hclk, 24000); + + /* [2] The voltage is set to 2.8V */ + regu = regulator_get(NULL, otp_data->regulator_name); + otp_voltage_saved = regulator_get_voltage(regu); + regulator_set_voltage(regu, 2800000, 2800000); + + /* [3] wait for BUSY and ERROR */ + err = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN); +out: + return err; +} + +static int otp_write_post(void) +{ + struct clk *hclk; + + hclk = clk_get(NULL, "hclk"); + + /* restore the clock and voltage */ + clk_set_rate(hclk, otp_hclk_saved); + regulator_set_voltage(regu, otp_voltage_saved, otp_voltage_saved); + otp_wait_busy(0); + + /* reset */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + return 0; +} +static void unmap_ocotp_addr(void) +{ +} + +#elif defined(CONFIG_ARCH_MX5) /* IMX5 below ============================= */ + +#include +#include +#include +#include "regs-ocotp-v2.h" + +static void *otp_base; +#define REGS_OCOTP_BASE ((unsigned long)otp_base) +#define HW_OCOTP_CUSTn(n) (0x00000030 + (n) * 0x10) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#define DEF_RELEX (15) /* > 10.5ns */ + +static int set_otp_timing(void) +{ + struct clk *apb_clk; + unsigned long clk_rate = 0; + unsigned long relex, sclk_count, rd_busy; + u32 timing = 0; + + /* [1] get the clock. It needs the AHB clock,though doc writes APB.*/ + apb_clk = clk_get(NULL, "ahb_clk"); + if (IS_ERR(apb_clk)) { + log("we can not find the clock"); + return -1; + } + clk_rate = clk_get_rate(apb_clk); + + /* do optimization for too many zeros */ + relex = clk_rate / (1000000000 / DEF_RELEX) + 1; + sclk_count = clk_rate / (1000000000 / 5000) + 1 + DEF_RELEX; + rd_busy = clk_rate / (1000000000 / 300) + 1; + + timing = BF(relex, OCOTP_TIMING_RELAX); + timing |= BF(sclk_count, OCOTP_TIMING_SCLK_COUNT); + timing |= BF(rd_busy, OCOTP_TIMING_RD_BUSY); + + __raw_writel(timing, REGS_OCOTP_BASE + HW_OCOTP_TIMING); + return 0; +} + +/* IMX5 does not need to open the bank anymore */ +static int otp_read_prepare(void) +{ + return set_otp_timing(); +} +static int otp_read_post(void) +{ + return 0; +} + +static int otp_write_prepare(struct mxc_otp_platform_data *otp_data) +{ + int ret = 0; + + /* [1] set timing */ + ret = set_otp_timing(); + if (ret) + return ret; + + /* [2] wait */ + otp_wait_busy(0); + return 0; +} +static int otp_write_post(void) +{ + /* Reload all the shadow registers */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(1); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + struct resource *res; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + otp_base = ioremap(res->start, SZ_8K); + if (!otp_base) { + log("Can not remap the OTP iomem!"); + return -1; + } + return 0; +} + +static void unmap_ocotp_addr(void) +{ + iounmap(otp_base); + otp_base = NULL; +} +#endif /* CONFIG_ARCH_MX5 */ +#endif diff --git a/drivers/char/regs-ocotp-v2.h b/drivers/char/regs-ocotp-v2.h new file mode 100755 index 000000000000..559c8e7fcec7 --- /dev/null +++ b/drivers/char/regs-ocotp-v2.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.12 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_TIMING (0x00000010) + +#define BP_OCOTP_TIMING_RSRVD0 22 +#define BM_OCOTP_TIMING_RSRVD0 0xFFC00000 +#define BF_OCOTP_TIMING_RSRVD0(v) \ + (((v) << 22) & BM_OCOTP_TIMING_RSRVD0) +#define BP_OCOTP_TIMING_RD_BUSY 16 +#define BM_OCOTP_TIMING_RD_BUSY 0x003F0000 +#define BF_OCOTP_TIMING_RD_BUSY(v) \ + (((v) << 16) & BM_OCOTP_TIMING_RD_BUSY) +#define BP_OCOTP_TIMING_RELAX 12 +#define BM_OCOTP_TIMING_RELAX 0x0000F000 +#define BF_OCOTP_TIMING_RELAX(v) \ + (((v) << 12) & BM_OCOTP_TIMING_RELAX) +#define BP_OCOTP_TIMING_SCLK_COUNT 0 +#define BM_OCOTP_TIMING_SCLK_COUNT 0x00000FFF +#define BF_OCOTP_TIMING_SCLK_COUNT(v) \ + (((v) << 0) & BM_OCOTP_TIMING_SCLK_COUNT) + +#define HW_OCOTP_DATA (0x00000020) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +#define HW_OCOTP_LOCK (0x00000030) + +#define BP_OCOTP_LOCK_UNALLOCATED 26 +#define BM_OCOTP_LOCK_UNALLOCATED 0xFC000000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 26) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_PIN 0x02000000 +#define BM_OCOTP_LOCK_DCPKEY_ALT 0x01000000 +#define BM_OCOTP_LOCK_SCC_ALT 0x00800000 +#define BM_OCOTP_LOCK_DCPKEY 0x00400000 +#define BM_OCOTP_LOCK_SWCAP_SHADOW 0x00200000 +#define BM_OCOTP_LOCK_SWCAP 0x00100000 +#define BM_OCOTP_LOCK_HWCAP_SHADOW 0x00080000 +#define BM_OCOTP_LOCK_HWCAP 0x00040000 +#define BM_OCOTP_LOCK_MAC_SHADOW 0x00020000 +#define BM_OCOTP_LOCK_MAC 0x00010000 +#define BM_OCOTP_LOCK_SJC_SHADOW 0x00008000 +#define BM_OCOTP_LOCK_SJC 0x00004000 +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00002000 +#define BM_OCOTP_LOCK_SRK 0x00001000 +#define BM_OCOTP_LOCK_SCC_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_SCC 0x00000400 +#define BM_OCOTP_LOCK_GP_SHADOW 0x00000200 +#define BM_OCOTP_LOCK_GP 0x00000100 +#define BM_OCOTP_LOCK_MEM_MISC_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_MEM_TRIM_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_MEM_TRIM 0x00000020 +#define BM_OCOTP_LOCK_CFG_MISC_SHADOW 0x00000010 +#define BM_OCOTP_LOCK_CFG_BOOT_SHADOW 0x00000008 +#define BM_OCOTP_LOCK_CFG_BOOT 0x00000004 +#define BM_OCOTP_LOCK_CFG_TESTER_SHADOW 0x00000002 +#define BM_OCOTP_LOCK_CFG_TESTER 0x00000001 + +/* + * multi-register-define name HW_OCOTP_CFGn + * base 0x00000040 + * count 7 + * offset 0x10 + */ +#define HW_OCOTP_CFGn(n) (0x00000040 + (n) * 0x10) +#define BP_OCOTP_CFGn_BITS 0 +#define BM_OCOTP_CFGn_BITS 0xFFFFFFFF +#define BF_OCOTP_CFGn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MEMn + * base 0x000000B0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_MEMn(n) (0x000000b0 + (n) * 0x10) +#define BP_OCOTP_MEMn_BITS 0 +#define BM_OCOTP_MEMn_BITS 0xFFFFFFFF +#define BF_OCOTP_MEMn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_GPn + * base 0x00000110 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_GPn(n) (0x00000110 + (n) * 0x10) +#define BP_OCOTP_GPn_BITS 0 +#define BM_OCOTP_GPn_BITS 0xFFFFFFFF +#define BF_OCOTP_GPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SCCn + * base 0x00000130 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SCCn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_SCCn_BITS 0 +#define BM_OCOTP_SCCn_BITS 0xFFFFFFFF +#define BF_OCOTP_SCCn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x000001B0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x000001b0 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SJC_RESPn + * base 0x00000230 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_SJC_RESPn(n) (0x00000230 + (n) * 0x10) +#define BP_OCOTP_SJC_RESPn_BITS 0 +#define BM_OCOTP_SJC_RESPn_BITS 0xFFFFFFFF +#define BF_OCOTP_SJC_RESPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MACn + * base 0x00000250 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10) +#define BP_OCOTP_MACn_BITS 0 +#define BM_OCOTP_MACn_BITS 0xFFFFFFFF +#define BF_OCOTP_MACn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x00000270 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x00000270 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x000002a0) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_SCS (0x000002b0) +#define HW_OCOTP_SCS_SET (0x000002b4) +#define HW_OCOTP_SCS_CLR (0x000002b8) +#define HW_OCOTP_SCS_TOG (0x000002bc) + +#define BM_OCOTP_SCS_LOCK 0x80000000 +#define BP_OCOTP_SCS_SPARE 1 +#define BM_OCOTP_SCS_SPARE 0x7FFFFFFE +#define BF_OCOTP_SCS_SPARE(v) \ + (((v) << 1) & BM_OCOTP_SCS_SPARE) +#define BM_OCOTP_SCS_HAB_JDE 0x00000001 + +#define HW_OCOTP_VERSION (0x000002c0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */