From: Ben Widawsky Date: Wed, 29 May 2013 02:22:26 +0000 (-0700) Subject: drm/i915: Add PM regs to pre/post install X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=eda63ffb906c2fb3b609a0e87aeb63c0f25b9e6b;p=linux-beck.git drm/i915: Add PM regs to pre/post install At the moment, these values are wiped out anyway by the rps enable/disable. That will be changed in the next patch though. v2: Add post install setup to address issue found by Damien in the next patch. replaced WARN_ON(dev_priv->rps.pm_iir != 0); with rps.pm_iir = 0; With the v2 of this patch and the deferred pm enabling (which changed since the original patches) we're now able to get PM interrupts before we've brought up enabled rps. At this point in boot, we don't want to do anything about it, so we simply ignore it. Since writing the original assertion, the code has changed quite a bit, and I believe removing this assertion is perfectly safe. Signed-off-by: Ben Widawsky Reviewed-by: Damien Lespiau [danvet: I don't agree with the justification to drop the WARN and added a FIXME to that effect.] Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d5bb8ce0fb4..b7e096008a9f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2522,6 +2522,11 @@ static void ivybridge_irq_preinstall(struct drm_device *dev) I915_WRITE(GTIER, 0x0); POSTING_READ(GTIER); + /* Power management */ + I915_WRITE(GEN6_PMIMR, 0xffffffff); + I915_WRITE(GEN6_PMIER, 0x0); + POSTING_READ(GEN6_PMIER); + if (HAS_PCH_NOP(dev)) return; @@ -2710,6 +2715,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) I915_WRITE(GTIER, render_irqs); POSTING_READ(GTIER); + /* Power management */ + I915_WRITE(GEN6_PMIMR, ~GEN6_PM_DEFERRED_EVENTS); + I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); + POSTING_READ(GEN6_PMIMR); + ibx_irq_postinstall(dev); return 0; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b676b578f70f..b1d0d0366fdf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3309,7 +3309,9 @@ static void gen6_enable_rps(struct drm_device *dev) /* requires MSI enabled */ I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); spin_lock_irq(&dev_priv->rps.lock); - WARN_ON(dev_priv->rps.pm_iir != 0); + /* FIXME: Our interrupt enabling sequence is bonghits. + * dev_priv->rps.pm_iir really should be 0 here. */ + dev_priv->rps.pm_iir = 0; I915_WRITE(GEN6_PMIMR, 0); spin_unlock_irq(&dev_priv->rps.lock); /* enable all PM interrupts */