From: Jianqun Date: Mon, 1 Sep 2014 21:56:28 +0000 (+0200) Subject: clk: rockchip: fix rk3288 pll status register location X-Git-Tag: v3.18-rc1~39^2~12^2~4 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=ee17eb83c48e04653d8b430735f82fd4cdac6ca3;p=karo-tx-linux.git clk: rockchip: fix rk3288 pll status register location In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: Jianqun Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Doug Anderson --- diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 21a5c74f1bec..12112899ff51 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -20,7 +20,7 @@ #include "clk.h" #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) -#define RK3288_GRF_SOC_STATUS 0x280 +#define RK3288_GRF_SOC_STATUS1 0x284 enum rk3288_plls { apll, dpll, cpll, gpll, npll, @@ -733,7 +733,7 @@ static void __init rk3288_clk_init(struct device_node *np) rockchip_clk_register_plls(rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), - RK3288_GRF_SOC_STATUS); + RK3288_GRF_SOC_STATUS1); rockchip_clk_register_branches(rk3288_clk_branches, ARRAY_SIZE(rk3288_clk_branches)); rockchip_clk_protect_critical(rk3288_critical_clocks,