From: Chen-Yu Tsai Date: Wed, 25 Mar 2015 21:04:47 +0000 (+0800) Subject: ARM: dts: sun6i: Set PLL6 as parent to AHB1 clock in AHB1 clock node X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f22fe1c5ab9f061b7e27e1eb31426d106deb1e22;p=linux-beck.git ARM: dts: sun6i: Set PLL6 as parent to AHB1 clock in AHB1 clock node On sun6i we already have PLL6 as AHB1 clock's parent. However this was previously set in the dma controller node, which takes effect when the dma controller is probed. We want this to take effect as soon as possible, so hrtimer rate calculation is correct, and to be sure the AHB1 clock rate remains as stable as possible. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 25a97f08d94b..60d912eeb7c7 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -241,6 +241,14 @@ reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; clock-output-names = "ahb1"; + + /* + * Clock AHB1 from PLL6, instead of CPU/AXI which + * has rate changes due to cpufreq. Also the DMA + * controller requires AHB1 clocked from PLL6. + */ + assigned-clocks = <&ahb1>; + assigned-clock-parents = <&pll6 0>; }; ahb1_gates: clk@01c20060 { @@ -426,10 +434,6 @@ clocks = <&ahb1_gates 6>; resets = <&ahb1_rst 6>; #dma-cells = <1>; - - /* DMA controller requires AHB1 clocked from PLL6 */ - assigned-clocks = <&ahb1>; - assigned-clock-parents = <&pll6 0>; }; mmc0: mmc@01c0f000 {