From: Heiner Kallweit Date: Tue, 15 Nov 2016 20:56:33 +0000 (+0100) Subject: spi: fsl-espi: set spi_master members min_speed_hz and max_speed_hz X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f254e65ce20fda3c442ebc50ae1502281963a79b;p=linux-beck.git spi: fsl-espi: set spi_master members min_speed_hz and max_speed_hz ESPI has a max and min supported SPI frequency, determined by the clock divider range. Set master->min_speed_hz/max_speed_hz to inform the SPI core about these limits. Then the SPI core handles cases where a transfer requests a frequency outside the supported range. So far the driver simply set the lowest supported frequency if the requested frequency was below the supported range. This is not necessarily an appropriate action as the device might not support frequencies greater than the requested one. With this patch the SPI core will reject transfers requesting a too low frequency. The check in fsl_espi_setup can be removed because the SPI core sets spi->max_speed_hz to master->max_speed_hz if it's not set already. Signed-off-by: Heiner Kallweit Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index 2635a33b8e98..4fbcc36fa891 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -314,13 +314,6 @@ static void fsl_espi_setup_transfer(struct spi_device *spi, if (pm > 15) { cs->hw_mode |= CSMODE_DIV16; pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; - - WARN_ONCE(pm > 15, - "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n", - dev_name(&spi->dev), hz, - espi->spibrg / (4 * 16 * (15 + 1))); - if (pm > 15) - pm = 15; } cs->hw_mode |= CSMODE_PM(pm); @@ -460,9 +453,6 @@ static int fsl_espi_setup(struct spi_device *spi) u32 loop_mode; struct fsl_espi_cs *cs = spi_get_ctldata(spi); - if (!spi->max_speed_hz) - return -EINVAL; - if (!cs) { cs = kzalloc(sizeof(*cs), GFP_KERNEL); if (!cs) @@ -673,6 +663,9 @@ static int fsl_espi_probe(struct device *dev, struct resource *mem, ret = -EINVAL; goto err_probe; } + /* determined by clock divider fields DIV16/PM in register SPMODEx */ + master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16); + master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4); init_completion(&espi->done);