From: Michael Hench Date: Tue, 26 Jul 2011 20:07:42 +0000 (-0500) Subject: mtd: eLBC NAND: update ecc_stats.corrected when lteccr available X-Git-Tag: next-20110818~40^2 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f54dd6aff1014250bda6465bd28d87cbb921be3e;p=karo-tx-linux.git mtd: eLBC NAND: update ecc_stats.corrected when lteccr available Signed-off-by: Michael Hench Acked-by: Scott Wood Signed-off-by: Artem Bityutskiy --- diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index acc27ee04749..eedd8ee2c9ac 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -243,6 +243,25 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) return -EIO; } + if (chip->ecc.mode != NAND_ECC_HW) + return 0; + + if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { + uint32_t lteccr = in_be32(&lbc->lteccr); + /* + * if command was a full page read and the ELBC + * has the LTECCR register, then bits 12-15 (ppc order) of + * LTECCR indicates which 512 byte sub-pages had fixed errors. + * bits 28-31 are uncorrectable errors, marked elsewhere. + * for small page nand only 1 bit is used. + * if the ELBC doesn't have the lteccr register it reads 0 + */ + if (lteccr & 0x000F000F) + out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ + if (lteccr & 0x000F0000) + mtd->ecc_stats.corrected++; + } + return 0; }