From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 2 Nov 2011 19:50:43 +0000 (-0600)
Subject: arm/tegra: Remove code that's ifndef CONFIG_ARM_GIC
X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f5ce5e7e9cc3f69c3e6a0a4599262f740aff92c0;p=linux-beck.git

arm/tegra: Remove code that's ifndef CONFIG_ARM_GIC

entry-macro.S contains some stale code for chips before Tegra20 that
apparently didn't use an ARM GIC. All chips supported by mainline use
an ARM GIC, so rip out the stale code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
---

diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c53889d..485a11eeaceb 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -15,7 +15,6 @@
 #include <mach/iomap.h>
 #include <mach/io.h>
 
-#if defined(CONFIG_ARM_GIC)
 #define HAVE_GET_IRQNR_PREAMBLE
 #include <asm/hardware/entry-macro-gic.S>
 
@@ -32,25 +31,3 @@
 
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
-#else
-	/* legacy interrupt controller for AP16 */
-	.macro	disable_fiq
-	.endm
-
-	.macro	get_irqnr_preamble, base, tmp
-	@ enable imprecise aborts
-	cpsie	a
-	@ EVP base at 0xf010f000
-	mov \base, #0xf0000000
-	orr \base, #0x00100000
-	orr \base, #0x0000f000
-	.endm
-
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
-	cmp \irqnr, #0x80
-	.endm
-#endif