From: Linus Torvalds Date: Fri, 1 Jun 2012 23:55:42 +0000 (-0700) Subject: Merge tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd X-Git-Tag: v3.5-rc1~8 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f5e7e844a571124ffc117d4696787d6afc4fc5ae;p=karo-tx-linux.git Merge tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd Pull mtd update from David Woodhouse: - More robust parsing especially of xattr data in JFFS2 - Updates to mxc_nand and gpmi drivers to support new boards and device tree - Improve consistency of information about ECC strength in NAND devices - Clean up partition handling of plat_nand - Support NAND drivers without dedicated access to OOB area - BCH hardware ECC support for OMAP - Other fixes and cleanups, and a few new device IDs Fixed trivial conflict in drivers/mtd/nand/gpmi-nand/gpmi-nand.c due to added include files next to each other. * tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd: (75 commits) mtd: mxc_nand: move ecc strengh setup before nand_scan_tail mtd: block2mtd: fix recursive call of mtd_writev mtd: gpmi-nand: define ecc.strength mtd: of_parts: fix breakage in Kconfig mtd: nand: fix scan_read_raw_oob mtd: docg3 fix in-middle of blocks reads mtd: cfi_cmdset_0002: Slight cleanup of fixup messages mtd: add fixup for S29NS512P NOR flash. jffs2: allow to complete xattr integrity check on first GC scan jffs2: allow to discriminate between recoverable and non-recoverable errors mtd: nand: omap: add support for hardware BCH ecc ARM: OMAP3: gpmc: add BCH ecc api and modes mtd: nand: check the return code of 'read_oob/read_oob_raw' mtd: nand: remove 'sndcmd' parameter of 'read_oob/read_oob_raw' mtd: m25p80: Add support for Winbond W25Q80BW jffs2: get rid of jffs2_sync_super jffs2: remove unnecessary GC pass on sync jffs2: remove unnecessary GC pass on umount jffs2: remove lock_super mtd: gpmi: add gpmi support for mx6q ... --- f5e7e844a571124ffc117d4696787d6afc4fc5ae diff --cc arch/arm/mach-omap1/board-fsample.c index c7364fdbda05,62a1e1122c30..6872f3fd400f --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@@ -199,10 -211,9 +197,9 @@@ static struct platform_nand_data nand_d .nr_chips = 1, .chip_offset = 0, .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --cc arch/arm/mach-omap1/board-h2.c index 7e503686f7af,9811b27ea169..a28e989a63f4 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@@ -195,11 -207,11 +193,10 @@@ static struct platform_nand_data h2_nan .nr_partitions = ARRAY_SIZE(h2_nand_partitions), .partitions = h2_nand_partitions, .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = h2_part_probes, }, .ctrl = { - .cmd_ctrl = h2_nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = h2_nand_dev_ready, - }, }; diff --cc arch/arm/mach-omap1/board-h3.c index 9fb03f189d93,94858dc8c840..108a8640fc6f --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@@ -197,10 -209,9 +195,9 @@@ static struct platform_nand_data nand_p .nr_partitions = ARRAY_SIZE(nand_partitions), .partitions = nand_partitions, .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, diff --cc arch/arm/mach-omap1/board-perseus2.c index f2cb24387c22,eb8b2c7d871e..703d55ecffe2 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@@ -157,10 -169,9 +155,9 @@@ static struct platform_nand_data nand_d .nr_chips = 1, .chip_offset = 0, .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --cc arch/arm/mach-omap2/gpmc.c index 46b09dae770e,1ca8d7fd625a..2286410671e7 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@@ -49,20 -49,8 +49,21 @@@ #define GPMC_ECC_CONTROL 0x1f8 #define GPMC_ECC_SIZE_CONFIG 0x1fc #define GPMC_ECC1_RESULT 0x200 + #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ +/* GPMC ECC control settings */ +#define GPMC_ECC_CTRL_ECCCLEAR 0x100 +#define GPMC_ECC_CTRL_ECCDISABLE 0x000 +#define GPMC_ECC_CTRL_ECCREG1 0x001 +#define GPMC_ECC_CTRL_ECCREG2 0x002 +#define GPMC_ECC_CTRL_ECCREG3 0x003 +#define GPMC_ECC_CTRL_ECCREG4 0x004 +#define GPMC_ECC_CTRL_ECCREG5 0x005 +#define GPMC_ECC_CTRL_ECCREG6 0x006 +#define GPMC_ECC_CTRL_ECCREG7 0x007 +#define GPMC_ECC_CTRL_ECCREG8 0x008 +#define GPMC_ECC_CTRL_ECCREG9 0x009 + #define GPMC_CS0_OFFSET 0x60 #define GPMC_CS_SIZE 0x30 diff --cc drivers/mtd/nand/gpmi-nand/gpmi-nand.c index b68e04310bd8,3eafc68154ed..a05b7b444d4f --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@@ -24,7 -24,8 +24,9 @@@ #include #include #include +#include + #include + #include #include "gpmi-nand.h" /* add our owner bbt descriptor */ diff --cc drivers/mtd/nand/mxc_nand.c index 9e374e9bd296,3310a48000d1..c58e6a93f445 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@@ -698,14 -751,33 +751,33 @@@ static void mxc_nand_select_chip_v1_v3( if (!host->clk_act) { /* Enable the NFC clock */ - clk_enable(host->clk); + clk_prepare_enable(host->clk); host->clk_act = 1; } + } - if (nfc_is_v21()) { - host->active_cs = chip; - writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); + static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) + { + struct nand_chip *nand_chip = mtd->priv; + struct mxc_nand_host *host = nand_chip->priv; + + if (chip == -1) { + /* Disable the NFC clock */ + if (host->clk_act) { + clk_disable(host->clk); + host->clk_act = 0; + } + return; + } + + if (!host->clk_act) { + /* Enable the NFC clock */ + clk_enable(host->clk); + host->clk_act = 1; } + + host->active_cs = chip; + writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); } /*