From: Jason Liu Date: Thu, 9 Feb 2012 06:09:58 +0000 (+0800) Subject: ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M X-Git-Tag: v3.0.35-fsl_4.1.0~1669 X-Git-Url: https://git.karo-electronics.de/?a=commitdiff_plain;h=f8aecebc7b06a3f489681ee8644f255d782171f7;p=karo-tx-linux.git ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu --- diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index c508b41d4730..5e703a8c9153 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5083,7 +5083,8 @@ static void clk_tree_init(void) reg = __raw_readl(MMDC_MDMISC_OFFSET); if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) == - (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) { + (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET) || + cpu_is_mx6dl()) { clk_set_parent(&periph_clk, &pll2_pfd_400M); printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n"); }