drivers: psci: make PSCI 1.0 functions initialization version dependent
The PSCI specifications [1] and the SMC calling convention mandate
that unimplemented functions ids must return NOT_SUPPORTED (0xffffffff)
if a function id is called but it is not implemented.
Consequently, PSCI 1.0 function ids that require the 1.0 PSCI_FEATURES
call to be initialized:
call the PSCI_FEATURES function id independently of the detected
PSCI firmware version, since, if the PSCI_FEATURES function id is not
implemented, it must return NOT_SUPPORTED according to the PSCI
specifications, causing the initialization functions to fail as expected.
Some existing PSCI implementations (ie Qemu PSCI emulation), do not
comply with the SMC calling convention and fail if function ids that are
not implemented are called from the OS, causing boot failures.
To solve this issue, this patch adds code that checks the PSCI firmware
version before calling PSCI 1.0 initialization functions so that the
OS makes sure that it is calling 1.0 functions only if the firmware
version detected is 1.0 or greater, therefore avoiding PSCI calls
that are bound to fail and might cause system boot failures owing
to non-compliant PSCI firmware implementations.
Olof Johansson [Thu, 22 Oct 2015 17:44:45 +0000 (10:44 -0700)]
Merge branch 'next/dt' into for-next
* next/dt:
ARM: mvebu: set SW polling as SDHCI card detection on A388-GP
arm: mvebu: reorder nodes under internal-regs by address in RN2120 .dts file
arm: mvebu: disable unused Armada RTC on ReadyNAS 102, 104 and 2120
ARM: mvebu: add DT support for Seagate Personal Cloud
ARM: mvebu: add DT support for Seagate NAS 2 and 4-Bay
Olof Johansson [Thu, 22 Oct 2015 17:43:03 +0000 (10:43 -0700)]
Merge tag 'mvebu-dt-4.4-2' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.4 (part 2)
- Add support for severals Armada-370-based Seagate NAS
- Fix Ready NAS device tree
- Modify SDHCI binding for A388-GP allowing using it on old and new
version of the board
* tag 'mvebu-dt-4.4-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: set SW polling as SDHCI card detection on A388-GP
arm: mvebu: reorder nodes under internal-regs by address in RN2120 .dts file
arm: mvebu: disable unused Armada RTC on ReadyNAS 102, 104 and 2120
ARM: mvebu: add DT support for Seagate Personal Cloud
ARM: mvebu: add DT support for Seagate NAS 2 and 4-Bay
Olof Johansson [Thu, 22 Oct 2015 17:06:05 +0000 (10:06 -0700)]
Merge branch 'next/cleanup' into for-next
* next/cleanup:
ARM: Remove __ref on hotplug cpu die path
ARM: Remove open-coded version of IRQCHIP_DECLARE
ARM: shmobile: R-Mobile: add missing of_node_put
ARM: shmobile: dt: Rename incorrect interrupt related binding
ARM: shmobile: apmu: correct type of CPU id
ARM: shmobile: r8a7779: Remove legacy PM Domain remainings
ARM: shmobile: r8a7778: Make r8a7778_init_irq_dt() static
ARM: shmobile: smp: Make shmobile_smp_apmu_cpu_shutdown() static
Olof Johansson [Thu, 22 Oct 2015 17:02:10 +0000 (10:02 -0700)]
Merge tag 'firmware/psci-1.0' of git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/linux into next/drivers
This pull request contains patches that enable PSCI 1.0 firmware
features for arm/arm64 platforms:
- Lorenzo Pieralisi adds support for the PSCI_FEATURES call, manages
various 1.0 specifications updates (power state id and functions return
values) and provides PSCI v1.0 DT bindings
- Sudeep Holla implements PSCI v1.0 system suspend support to enable PSCI
based suspend-to-RAM
* tag 'firmware/psci-1.0' of git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/linux:
drivers: firmware: psci: add system suspend support
drivers: firmware: psci: define more generic PSCI_FN_NATIVE macro
drivers: firmware: psci: add PSCI v1.0 DT bindings
drivers: firmware: psci: add extended stateid power_state support
drivers: firmware: psci: add PSCI_FEATURES call
drivers: firmware: psci: move power_state handling to generic code
drivers: firmware: psci: add INVALID_ADDRESS return value
Stephen Boyd [Mon, 19 Oct 2015 20:05:33 +0000 (13:05 -0700)]
ARM: Remove __ref on hotplug cpu die path
Now that __cpuinit has been removed, the __ref markings on these
functions are useless. Remove them. This also reduces the size of
the multi_v7_defconfig image:
Sudeep Holla [Fri, 16 Oct 2015 16:01:36 +0000 (17:01 +0100)]
ARM: dts: fix gpio-keys wakeup-source property
The keyboard driver for GPIO buttons(gpio-keys) checks for one of the
two boolean properties to enable gpio buttons as wakeup source:
1. "wakeup-source" or
2. the legacy "gpio-key,wakeup"
However juno, ste-snowball and emev2-kzm9d dts file have a undetected
"wakeup" property to indictate the wakeup source.
This patch fixes it by making use of "wakeup-source" property.
Cc: Magnus Damm <magnus.damm@gmail.com> Acked-by: Simon Horman <horms@verge.net.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Marc Zyngier [Fri, 16 Oct 2015 14:21:10 +0000 (15:21 +0100)]
ARM: Remove open-coded version of IRQCHIP_DECLARE
Now that the IRQCHIP_DECLARE macro has been moved to linux/irqchip.h,
it becomes possible to cleanup the open-coded versions of the same
macro that have been added to some private irqchips implementations.
Cc: Sascha Hauer <kernel@pengutronix.de> Acked-by: Kukjin Kim <kgene@kernel.org> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Thu, 22 Oct 2015 16:48:02 +0000 (09:48 -0700)]
Merge tag 'renesas-cleanup2-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Second Round of Renesas ARM Based SoC Cleanup for v4.4
* Remove now unused legacy pm domain code
* Add missing of_node_put to pm-rmobile
* Corresct spelling of interrupt-names in renesas-memory-controller binding
documentation
* Correct signdness of CPU id in shmobile apmu implementation
* Make some functions static as appropriate
* tag 'renesas-cleanup2-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: add missing of_node_put
ARM: shmobile: dt: Rename incorrect interrupt related binding
ARM: shmobile: apmu: correct type of CPU id
ARM: shmobile: r8a7779: Remove legacy PM Domain remainings
ARM: shmobile: r8a7778: Make r8a7778_init_irq_dt() static
ARM: shmobile: smp: Make shmobile_smp_apmu_cpu_shutdown() static
Antoine Tenart [Wed, 14 Oct 2015 14:02:50 +0000 (16:02 +0200)]
ARM: multi_v7_defconfig: improve multi_v7_defconfig support for Berlin
Some drivers used on a Marvell Berlin kernel were missing from
multi_v7_defconfig. This series add them:
* The pxa168 Ethernet driver is added as a loadable module.
* The Berlin ADC driver is added as a loadable module.
* Both the Berlin USB PHY and SATA PHY drivers are added,
built-in, as they are required for the already available USB
and SATA functionalities in multi_v7_defconfig.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Arnd Bergmann [Wed, 21 Oct 2015 15:01:14 +0000 (17:01 +0200)]
Merge tag 'omap-for-v4.3/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "Fixes for omaps for v4.3-rc cycle" from Tony Lindgren:
- Fix oops with LPAE and moew than 2GB of memory by enabling
ZONE_DMA for LPAE. Probably no need for stable on this one as we
only recently ran into this with the mainline kernel
- Fix imprecise external abort caused by bogus SRAM init. This affects
dm814x recently merged, so no need for stable on this one AFAIK
* tag 'omap-for-v4.3/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix imprecise external abort caused by bogus SRAM init
ARM: OMAP2+: Fix oops with LPAE and more than 2GB of memory
Some omaps are producing imprecise external aborts because we are
wrongly trying to init SRAM for device tree based booting. Only
omap3 is still using the legacy SRAM code, so we need to make it
omap3 specific. Otherwise we can get errors like this on at least
dm814x:
Unhandled fault: imprecise external abort (0xc06) at 0xc08b156c
...
(omap_rev) from [<c08b12e0>] (omap_sram_init+0xf8/0x3e0)
(omap_sram_init) from [<c08aca0c>] (omap_sdrc_init+0x10/0xb0)
(omap_sdrc_init) from [<c08b581c>] (pdata_quirks_init+0x18/0x44)
(pdata_quirks_init) from [<c08b5478>] (omap_generic_init+0x10/0x1c)
(omap_generic_init) from [<c08a57e0>] (customize_machine+0x1c/0x40)
(customize_machine) from [<c00098a4>] (do_one_initcall+0x80/0x1dc)
(do_one_initcall) from [<c08a2ec4>] (kernel_init_freeable+0x218/0x2e8)
(kernel_init_freeable) from [<c063a554>] (kernel_init+0x8/0xec)
(kernel_init) from [<c000f890>] (ret_from_fork+0x14/0x24)
Let's fix the issue by making sure omap_sdrc_init only gets called for
omap3. To do that, we need to have compatible "ti,omap3" in the dts
files. And let's also use "ti,omap3630" instead of "ti,omap36xx" like
we're supposed to.
Sudip Mukherjee [Fri, 16 Oct 2015 23:08:56 +0000 (08:08 +0900)]
thermal: exynos: Fix register read in TMU
The value of emul_con was getting overwritten if the selected soc is
SOC_ARCH_EXYNOS5260. And so as a result we were reading from the wrong
register in the case of SOC_ARCH_EXYNOS5260.
Fixes: 488c7455d74c ("thermal: exynos: Add the support for Exynos5433 TMU") Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
Tony Lindgren [Fri, 16 Oct 2015 19:16:21 +0000 (12:16 -0700)]
ARM: OMAP2+: Fix oops with LPAE and more than 2GB of memory
On boards with more than 2GB of RAM booting goes wrong with things not
working and we're getting lots of l3 warnings:
WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147
l3_interrupt_handler+0x260/0x384() 44000000.ocp:L3 Custom Error: MASTER MMC6 TARGET DMM1 (Idle):
Data Access in User mode during Functional access
...
[<c044e158>] (scsi_add_host_with_dma) from [<c04705c8>]
(ata_scsi_add_hosts+0x5c/0x18c)
[<c04705c8>] (ata_scsi_add_hosts) from [<c046b13c>]
(ata_host_register+0x150/0x2cc)
[<c046b13c>] (ata_host_register) from [<c046b38c>]
(ata_host_activate+0xd4/0x124)
[<c046b38c>] (ata_host_activate) from [<c047f42c>]
(ahci_host_activate+0x5c/0x194)
[<c047f42c>] (ahci_host_activate) from [<c0480854>]
(ahci_platform_init_host+0x1f0/0x3f0)
[<c0480854>] (ahci_platform_init_host) from [<c047c9dc>]
(ahci_probe+0x70/0x98)
[<c047c9dc>] (ahci_probe) from [<c04220cc>]
(platform_drv_probe+0x54/0xb4)
Let's fix the issue by enabling ZONE_DMA for LPAE. Note that we need to
limit dma_zone_size to 2GB as the rest of the RAM is beyond the 4GB limit.
Let's also fix things for dra7 as done in similar patches in the TI tree
by Lokesh Vutla <lokeshvutla@ti.com>.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Marcin Wojtas [Thu, 15 Oct 2015 16:25:44 +0000 (18:25 +0200)]
ARM: mvebu: set SW polling as SDHCI card detection on A388-GP
The newest revisions of A388-GP (v1.5 and higher) support only
DAT3-based card detection. Revisions < v1.5 based on GPIO detection
via I2C expander, but this solution is supposed to be deprecated on
new boards. In order to satisfy all type of hardware this commit
changes card detection to use software polling mechanism. Also a
comment is added on possible card detection options in A388-GP
DT board file.
Signed-off-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Arnd Bergmann [Thu, 15 Oct 2015 21:19:21 +0000 (23:19 +0200)]
Merge branches 'fixes', 'next/fixes-non-critical', 'next/cleanup', 'next/soc' and 'next/defconfig' into for-next
* fixes:
ARM: tegra: Comment out gpio-ranges properties
* next/fixes-non-critical:
MAINTAINERS: update lpc18xx entry with more drivers
* next/cleanup:
ARM: OMAP3: clock: remove un-used core dpll re-program code
ARM: OMAP2+: Remove unneeded semicolons
ARM: OMAP3: vc: Remove unused macros
ARM: OMAP1: Remove board support for VoiceBlue board
ARM: OMAP2+: Remove legacy OMAP3 ISP instantiation
ARM: mvebu: Use a CR_C constant instead of a hard-coded one
* next/soc:
ARM: digicolor: select pinctrl/gpio driver
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
ARM: brcmstb: Setup BIU control registers during boot
soc: brcmstb: Add Bus Interface Unit control setup
ARM: mvebu: add support to clear shared L2 bit on Armada XP
ARM: berlin: register cpufreq-dt
arm64: berlin: enable ARCH_REQUIRE_GPIOLIB
soc: add stubs for brcmstb SoC's
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
Arnd Bergmann [Thu, 15 Oct 2015 21:09:17 +0000 (23:09 +0200)]
Merge tag 'qcom-arm64-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm into next/dt
Pull "Qualcomm ARM64 Updates for v4.4" from Andy Gross:
* Add RNG device tree node
* Add MSM8x16 serial UART1 node
* Enable eMMC on apq8016-sbc board
* Fix I2C pinconf sleep state function
* Add MSM8916 I2C nodes
* Enable I2C busses on LS and HS on APQ8016-sbc
* Enable SPI busses on LS and HS on APQ8016-sbc
* tag 'qcom-arm64-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm:
arm64: dts: apq8016-sbc: enable spi buses on LS and HS
arm64: dts: apq8016-sbc: enable i2c buses on LS and HS
arm64: dts: qcom: Add msm8916 I2C nodes.
arm64: dts: fix i2c pinconf sleep state function
arm64: dts: qcom: Enable eMMC on apq8016-sbc board
arm64: dts: qcom: Add 8x16 Serial UART1 node
arm64: dts: qcom: Add RNG device tree node
Arnd Bergmann [Tue, 13 Oct 2015 15:05:39 +0000 (17:05 +0200)]
soc: qcom/smem: add HWSPINLOCK dependency
This fixes a build error when smem is enabled without hwspinlock:
drivers/built-in.o: In function `qcom_smem_alloc':
rockchip-efuse.c:(.text+0x7a3e4): undefined reference to `__hwspin_lock_timeout'
rockchip-efuse.c:(.text+0x7a568): undefined reference to `__hwspin_unlock'
drivers/built-in.o: In function `qcom_smem_remove':
rockchip-efuse.c:(.text+0x7a5cc): undefined reference to `hwspin_lock_free'
drivers/built-in.o: In function `qcom_smem_probe':
rockchip-efuse.c:(.text+0x7a960): undefined reference to `hwspin_lock_request_specific'
rockchip-efuse.c:(.text+0x7a988): undefined reference to `of_hwspin_lock_get_id'
drivers/built-in.o: In function `qcom_smem_get':
rockchip-efuse.c:(.text+0x7aa24): undefined reference to `__hwspin_lock_timeout'
rockchip-efuse.c:(.text+0x7aafc): undefined reference to `__hwspin_unlock'
Arnd Bergmann [Thu, 15 Oct 2015 21:03:24 +0000 (23:03 +0200)]
Merge tag 'qcom-soc-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm into next/drivers
Pull "Qualcomm ARM Based SoC Updates for 4.4" from Andy Gross:
* Implement id_table driver matching in SMD
* Avoid NULL pointer exception on remove of SMEM
* Reorder SMEM/SMD configs
* Make qcom_smem_get() return a pointer
* Handle big endian CPUs correctly in SMEM
* Represent SMD channel layout in structures
* Use __iowrite32_copy() in SMD
* Remove use of VLAIs in SMD
* Handle big endian CPUs correctly in SMD/RPM
* Handle big endian CPUs corretly in SMD
* Reject sending SMD packets that are too large
* Fix endianness issue in SCM __qcom_scm_is_call_available
* Add missing prototype for qcom_scm_is_available()
* Correct SMEM items for upper channels
* Use architecture level to build SCM correctly
* Delete unneeded of_node_put in SMD
* Correct active/slep state flagging in SMD/RPM
* Move RPM message ram out of SMEM DT node
* tag 'qcom-soc-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm:
soc: qcom: smem: Move RPM message ram out of smem DT node
soc: qcom: smd-rpm: Correct the active vs sleep state flagging
soc: qcom: smd: delete unneeded of_node_put
firmware: qcom-scm: build for correct architecture level
soc: qcom: smd: Correct SMEM items for upper channels
qcom-scm: add missing prototype for qcom_scm_is_available()
qcom-scm: fix endianess issue in __qcom_scm_is_call_available
soc: qcom: smd: Reject send of too big packets
soc: qcom: smd: Handle big endian CPUs
soc: qcom: smd_rpm: Handle big endian CPUs
soc: qcom: smd: Remove use of VLAIS
soc: qcom: smd: Use __iowrite32_copy() instead of open-coding it
soc: qcom: smd: Represent channel layout in structures
soc: qcom: smem: Handle big endian CPUs
soc: qcom: Make qcom_smem_get() return a pointer
soc: qcom: Reorder SMEM/SMD configs
soc: qcom: smem: Avoid NULL pointer exception on remove
soc: qcom: smd: Implement id_table driver matching
Arnd Bergmann [Thu, 15 Oct 2015 20:55:53 +0000 (22:55 +0200)]
Merge tag 'berlin-soc-for-4.4-2' of git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Merge "Marvell Berlin SoC for 4.4 take 2" from Sebastian Hesselbarth:
- use the non-self-clearing reset register
- add cpu hotplug support
* tag 'berlin-soc-for-4.4-2' of git://git.infradead.org/users/hesselba/linux-berlin:
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
Arnd Bergmann [Thu, 15 Oct 2015 20:38:10 +0000 (22:38 +0200)]
Merge tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Merge "SCPI support on ARM64 Juno Development Platform" from Sudeep Holla:
1. SRAM, MHU mailbox and SCPI support
2. CPU topology using cpu-map
3. Clock support for all the cpus
4. Support for SoC sensors
* tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: Add sensor node to Juno dt
arm64: dts: add clock support for all the cpus
arm64: dts: add CPU topology on Juno
arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
Arnd Bergmann [Thu, 15 Oct 2015 20:26:03 +0000 (22:26 +0200)]
Merge tag 'drivers_pl172_for_4.4' of https://github.com/manabian/linux-lpc into next/drivers
Merge "PL172 driver updates for v4.4" from Joachim Eastwood:
Support for additional ARM MPMCs to the PL172 driver and an update to
the bindings documentation to reflect this from Vladimir Zapolskiy.
"The change adds support of ARM PrimeCell PL175 MPMC and PL176 MPMC,
the static memory controllers on devices are similar to one found on
ARM PrimeCell PL172, add support to the existing driver."
* tag 'drivers_pl172_for_4.4' of https://github.com/manabian/linux-lpc:
doc: dt: arm,pl172: add description of PL175 and PL176 controllers
memory: pl172: add ARM PrimeCell PL176 MPMC support
memory: pl172: add ARM PrimeCell PL175 MPMC support
memory: pl172: correct MPMC peripheral ID register bits
Joachim Eastwood [Sun, 11 Oct 2015 20:40:41 +0000 (22:40 +0200)]
ARM: configs: update lpc18xx defconfig
- Enable SPIFI Flash and JFFS2 to support rootfs on Flash memory
- Enable USB Phy, mass storage and SCSI to support USB memory
- Enable PCF857x and JC42 I2C devices found on Hitex board
- Enable PL172 to support memory mapped NOR Flash
- New LPC18xx drivers: I2C, Watchdog, SCT PWM and RTC
Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 15 Oct 2015 20:22:26 +0000 (22:22 +0200)]
Merge tag 'keystone-driver-soc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/soc
Merge "ARM Keystone SOC driver updates for 4.4" from Santosh Shilimkar:
Documentation and support to be able to load the PDSP
firmware necessary for accumulator operation.
* tag 'keystone-driver-soc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
Arnd Bergmann [Thu, 15 Oct 2015 20:09:07 +0000 (22:09 +0200)]
Merge tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux into next/soc
Merge "Broadcom soc changes for v4.4 (try 2)" from Florian Fainelli:
This pull request contains the following Broadcom SoC platform and driver changes:
- Brian Norris create a drivers/soc/brcmstb/ stub as a place holder for SoC-specific
code which is coming next
- Florian Fainelli adds support for configuring the BCM7xxx SoCs Bus Interface Unit
with their specific write-pairing setting, which must be saved and restored during
system-wide suspend/resume, and consequently updates the brcmstb machine code to
initialize the BIU
- Jon Mason adds support for the Northstar Plus SoCs by introducing a custom machine
descriptor matching their compatible string and setting up the PL310 L2 cache and
enabling the relevant ARM errata for their Cortex-A9
* tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux:
ARM: brcmstb: Setup BIU control registers during boot
soc: brcmstb: Add Bus Interface Unit control setup
soc: add stubs for brcmstb SoC's
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
Add cpu hotplug support for berlin SoCs such as BG2 and BG2Q. These SoC
don't support power off cpu independently, but we also want cpu hotplug
support in these SoCs. We achieve this goal by putting the dying CPU in
WFI state after the coherency is disabled, then asserting the dying CPU
reset bit to put the CPU in reset state.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
arm: berlin: use non-self-cleared reset register to reset cpu
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next hotplug commit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Antoine Tenart [Thu, 15 Oct 2015 18:55:55 +0000 (20:55 +0200)]
clk: berlin: add cpuclk
Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider
fixed to 1.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Thierry Reding [Fri, 9 Oct 2015 15:51:47 +0000 (17:51 +0200)]
ARM: tegra: Comment out gpio-ranges properties
While the addition of these properties is technically correct it unveils
a bug with deferred probe. The problem is that the presence of the gpio-
range property causes the gpio-tegra driver to defer probe (it needs the
pinctrl driver to be ready). That's technically correct, but it causes a
couple of issues:
- The keyboard on Chromebooks stops working. The reason for that is
that the gpio-tegra device has not registered an IRQ domain by the
time the EC SPI device is registered, hence the interrupt number
resolves to 0. This is technically a bug in the SPI core, since it
should really resolve the interrupt at probe time and defer if the
IRQ domain isn't available yet. This is similar to what's done for
I2C and platform device already.
- The gpio-tegra device deferring probe means that it is moved to the
end of the dpm_list. This list defines the suspend/resume order for
devices. However the core lacks a way to move all users of the
gpio-tegra device to the end of the dpm_list at the same time. This
in turn results in a subtle bug on Jetson TK1, where the gpio-keys
device is used to expose the power key as input. The power key is a
convenient way to wake the system from suspend. Interestingly, the
gpio-keys device ends up getting probed at a point after gpio-tegra
has been probed successfully from having been deferred earlier. As
such the driver doesn't need to defer the probe itself, and hence
the device isn't moved to the end of the dpm_list. This causes the
gpio-tegra device to be suspended before gpio-keys, which in turn
leaves gpio-keys unable to wake the system from suspend.
There are patches in the works to fix both of the above issues, but they
are too involved to make it into v4.3, so in the meantime let's fix the
regressions by commenting out the gpio-ranges properties until the fixes
have landed.
Arnd Bergmann [Thu, 15 Oct 2015 15:56:04 +0000 (17:56 +0200)]
Merge branches 'fixes' and 'next/dt' into for-next
* fixes:
ARM: dts: uniphier: fix IRQ number for devices on PH1-LD6b ref board
drivers/perf: arm_pmu: avoid CPU device_node reference leak
bus: arm-ccn: Fix irq affinity setting on CPU migration
bus: arm-ccn: Handle correctly no-more-cpus case
ARM: meson6: DTS: Fix wrong reg mapping and IRQ numbers
Documentation: ARM: List new omap MMC requirements
memory: omap-gpmc: dump "before" state before first modification
memory: omap-gpmc: Fix unselectable debug option for GPMC
ARM: dts: am57xx-beagle-x15: set VDD_SD to always-on
* next/dt: (29 commits)
ARM64: juno: add NOR flash to device tree
ARM: dts: uniphier: change the external bus address mapping
ARM: dts: msm8974: fix typo in "disabled" property
ARM: dts: qcom-pm8941: Add charger node
dt-binding: power: Add Qualcomm SMBB binding
arm: dts: qcom: Add #power-domain-cells property
ARM: dts: qs600: Add SD card detect support.
ARM: dts: apq8064-ifc6410: add notify led support.
ARM: dts: qs600: add pwrseq support to WLAN
ARM: dts: ifc6410: Add pwrseq support for WLAN
ARM: dts: qs600: Add missing pinctrl property for gsbi7 uart
ARM: dts: ifc6410: Add missing pinctrl to gsbi7 uart
ARM: dts: apq8064: add missing gsbi7 uart pinctrl
ARM: dts: apq8064: Prefix the gsbi6 uart pins correctly
ARM: dts: apq8064: add pm8921 pwrkey support
ARM: dts: apq8064: add pm8921 rtc
ARM: dts: qs600: remove unnecessary eeprom label
ARM: dts: ifc6410: remove unnecessary eeprom label
ARM: dts: apq8064: remove redundant i2c pinctrl properties
ARM: dts: qcom: Remove extra reg element from iadc device
...
Arnd Bergmann [Thu, 15 Oct 2015 15:21:01 +0000 (17:21 +0200)]
Merge tag 'qcom-dt-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm into next/dt
Pull "Qualcomm ARM Based Device Tree Updates for v4.4" from Andy Gross:
* Add DT binding document for SMEM
* Add SMD, RPM, and Regulator nodes on MSM8974
* Remove extra reg element from iadc device
* Remove redunandant i2c pinctrl properties on APQ8064
* Remove unnecessary eeprom label on IFC6410
* Remove unnecessary eeprom label from QS600
* Add PM8921 RTC support on APQ8064
* Add PM8921 pwrkey support on APQ8064
* Prefix GSBI6 uart pins on APQ8064 correctly
* Add missing GSBI7 uart pinctrl on APQ8064
* Add missing GSBI7 uart pinctrl on IFC6410
* Add missing GSBI7 pinctrl uart property on QS600
* Add pwrseq support for WLAN on IFC6410
* Add pwrseq support for WLAN on QS600
* Add notify led support on IFC6410
* Add SD card detect support onQS600
* Add #power-domain-cells property to documentation
* Add Qualcomm SMBB binding document
* Add PM8941 charge node
* Fix typo in disabled property on MSM8974
* tag 'qcom-dt-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm:
ARM: dts: msm8974: fix typo in "disabled" property
ARM: dts: qcom-pm8941: Add charger node
dt-binding: power: Add Qualcomm SMBB binding
arm: dts: qcom: Add #power-domain-cells property
ARM: dts: qs600: Add SD card detect support.
ARM: dts: apq8064-ifc6410: add notify led support.
ARM: dts: qs600: add pwrseq support to WLAN
ARM: dts: ifc6410: Add pwrseq support for WLAN
ARM: dts: qs600: Add missing pinctrl property for gsbi7 uart
ARM: dts: ifc6410: Add missing pinctrl to gsbi7 uart
ARM: dts: apq8064: add missing gsbi7 uart pinctrl
ARM: dts: apq8064: Prefix the gsbi6 uart pins correctly
ARM: dts: apq8064: add pm8921 pwrkey support
ARM: dts: apq8064: add pm8921 rtc
ARM: dts: qs600: remove unnecessary eeprom label
ARM: dts: ifc6410: remove unnecessary eeprom label
ARM: dts: apq8064: remove redundant i2c pinctrl properties
ARM: dts: qcom: Remove extra reg element from iadc device
ARM: dts: msm8974: Add smd, rpm and regulator nodes
soc: qcom: Add device tree binding for SMEM
Linus Walleij [Thu, 15 Oct 2015 10:20:15 +0000 (12:20 +0200)]
ARM64: juno: add NOR flash to device tree
The Juno motherboard has a NOR flash on the motherboard, enable
this to be accessed with the CFI flash driver. Results after
enabling MTD, MTD_CFI, MTD_PHYSMAP, MTD_PHYSMAP_OF,
MTD_CFI_INTELEXT:
8000000.flash: Found 2 x16 devices at 0x0 in 32-bit bank.
Manufacturer ID 0x000089 Chip ID 0x008919
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Using buffer write method
Using auto-unlock on power-up/resume
cfi_cmdset_0001: Erase suspend on write enabled
erase region 0: offset=0x0,size=0x40000,blocks=255
erase region 1: offset=0x3fc0000,size=0x10000,blocks=4
Masahiro Yamada [Thu, 15 Oct 2015 09:05:32 +0000 (18:05 +0900)]
ARM: dts: uniphier: change the external bus address mapping
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
0x00000000 - 0x0fffffff
0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.
In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.
For the consistency, use the latter for all the SoCs.
Also, fix the range properties to reflect the real address mapping,
where the support card is located at the offset address 0x01f00000
of CS1 of the external bus.
Arnd Bergmann [Thu, 15 Oct 2015 15:13:26 +0000 (17:13 +0200)]
Merge tag 'omap-for-v4.3/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "Fixes for omap against v4.3-rc5" from Tony Lindgren:
- Regulator fix for beagle-x15 to fix HDMI without a SD card being
inserted
- GPMC fix for showing proper timings and to allow enabling debug
options that somehow was unselectable earlier
- Add minimal documentation for new MMC1 dependency on
REGULATOR_PBIAS as it may not be obvious for people with
targeted .config files
* tag 'omap-for-v4.3/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
Documentation: ARM: List new omap MMC requirements
memory: omap-gpmc: dump "before" state before first modification
memory: omap-gpmc: Fix unselectable debug option for GPMC
ARM: dts: am57xx-beagle-x15: set VDD_SD to always-on
Pawel Moll [Thu, 15 Oct 2015 13:32:46 +0000 (14:32 +0100)]
bus: arm-ccn: Fix irq affinity setting on CPU migration
When PMU context is migrating between CPUs, interrupt affinity is set as
well. Only this should not happen when the CCN interrupt is not being
used at all (the driver is using a hrtimer tick instead).
Pawel Moll [Thu, 15 Oct 2015 13:32:45 +0000 (14:32 +0100)]
bus: arm-ccn: Handle correctly no-more-cpus case
When migrating events the driver picks another cpu using
cpumask_any_but() function, which returns value >= nr_cpu_ids
when there is none available, not a negative value as the code
assumed. Fixed now.
Lucas Stach [Wed, 14 Oct 2015 14:48:32 +0000 (16:48 +0200)]
ARM: mvebu: remove the workaround imprecise abort fault handler
This is not needed anymore. Handling a potentially pending imprecise
external abort left behind by the bootloader is now done in a slightly
safer way inside the common ARM startup code.
[gregory.clement@free-electrons.com: Beside the Armada 375 Z1 which
initially required this, is no more supported]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Marcin Wojtas [Thu, 15 Oct 2015 01:17:08 +0000 (03:17 +0200)]
ARM: mvebu: correct a385-db-ap compatible string
This commit enables standby support on Armada 385 DB-AP board, because
the PM initalization routine requires "marvell,armada380" compatible
string for all Armada 38x-based platforms.
Beside the compatible "marvell,armada38x" was wrong and should be fixed
in the stable kernels too.
[gregory.clement@free-electrons.com: add information, about the fixes] Fixes: e5ee12817e9ea ("ARM: mvebu: Add Armada 385 Access Point
Development Board support") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: <stable@vger.kernel.org>
Stephen Boyd [Thu, 8 Oct 2015 18:34:09 +0000 (13:34 -0500)]
soc: qcom: smem: Move RPM message ram out of smem DT node
SMEM is a software construct built on top of a DDR reserved region
and sometimes a device memory region called RPM message ram. Having
the RPM message ram in the smem DT node's reg property leads to the
smem node being located in different places depending on if the
message ram is being used or not. Let's add a qcom specific
property, qcom,rpm-msg-ram, and point to the device memory from
the SMEM node via a phandle. As SMEM is a software construct, it
really needs to reside at the root of the DT regardless of whether
it's using the message ram or not.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
Arnd Bergmann [Mon, 12 Oct 2015 14:56:19 +0000 (16:56 +0200)]
firmware: qcom-scm: build for correct architecture level
The ".arch_extension sec" directive is only available on ARMv6 or higher,
so if we enable the SCM driver while building a kernel for an older CPU,
we get a build error:
/tmp/ccUyhMOY.s:130: Error: selected processor does not support ARM mode `smc #0'
/tmp/ccUyhMOY.s:216: Error: selected processor does not support ARM mode `smc #0'
/tmp/ccUyhMOY.s:373: Error: selected processor does not support ARM mode `smc #0'
make[4]: *** [drivers/firmware/qcom_scm-32.o] Error 1
This changes the Makefile so we pass the ARMv7 architecture level both
for the check and for the actual compilation of the scm driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andy Gross <agross@codeaurora.org>
Attempting to find room for a packet that's bigger than the fifo will
never succeed and the calling process will be sleeping forever in the
loop, waiting for enough room. So fail early instead.
Reported-by: Courtney Cavin <courtney.cavin@sonymobile.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Thu, 17 Sep 2015 21:50:53 +0000 (14:50 -0700)]
soc: qcom: smd: Handle big endian CPUs
The smd structures are always in little endian, but the smd
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Wed, 2 Sep 2015 22:46:50 +0000 (15:46 -0700)]
soc: qcom: smd_rpm: Handle big endian CPUs
The smd rpm structures are always in little endian, but this
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Wed, 2 Sep 2015 22:46:48 +0000 (15:46 -0700)]
soc: qcom: smd: Remove use of VLAIS
Usage of VLAIS prevents clang from compiling this file, and it
also opens us to the possibility of allocating a large structure
on the stack to the point that we blow past the limit of the
kernel stack. Remove the VLAIS and allocate a structure on the
heap with kmalloc so that we're safer and more clang friendly.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Wed, 2 Sep 2015 22:46:46 +0000 (15:46 -0700)]
soc: qcom: smd: Represent channel layout in structures
The rx and tx channel info are laid out in memory next to each
other, and there are two types of channel info structures, byte
based and word based. We have 4 pointers to these info
structures, when we really only need two to point to the
different types of structures. Encapsulate the byte based and
word based tx/rx structures in a "channel pair" structure that
describes the layout of memory and reduces the number of pointers
in the smd channel structure by two.
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Wed, 2 Sep 2015 22:46:45 +0000 (15:46 -0700)]
soc: qcom: smem: Handle big endian CPUs
The contents of smem are always in little endian, but the smem
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Wed, 2 Sep 2015 22:46:44 +0000 (15:46 -0700)]
soc: qcom: Make qcom_smem_get() return a pointer
Passing a void ** almost always requires a cast at the call site.
Instead of littering the code with casts every time this function
is called, have qcom_smem_get() return a void pointer to the
location of the smem item. This frees the caller from having to
cast the pointer.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Stephen Boyd [Fri, 28 Aug 2015 18:23:33 +0000 (11:23 -0700)]
soc: qcom: Reorder SMEM/SMD configs
When I make nconfig, having the SMEM option after the SMD option
causes the configurator to get confused when I'm enabling and
disabling these options. Let's move SMEM before SMD so there's a
clear indented dependency chain.
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Implement a id_table based driver maching mechanism for drivers that
binds to fixed channels and doesn't need any additional configuration,
e.g. IPCRTR and DIAG.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
Remove the OMAP3 core DPLL re-program code, and the associated SRAM
code that does the low-level programming of the DPLL divider, idling
of the SDRAM etc.
This code was never fully implemented in the kernel; things missing
were driver side handling of core clock changes (they need to account
for their functional clock rate being changed on-the-fly), and the whole
framework required for handling this. Thus, there is not much point
to keep carrying the low-level support code either.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
projects / karo-tx-linux.git / log