Paul Mundt [Mon, 10 Dec 2007 06:50:28 +0000 (15:50 +0900)]
sh: Encode L1/L2 cache shape in auxvt.
This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.
Thomas Betker [Fri, 30 Nov 2007 09:22:10 +0000 (18:22 +0900)]
sh: Fix up uImage target entry point.
This patch changes the uImage target so that it generates a wrapped
compressed vmlinux, rather than a wrapped zImage. The previous version
matched the ARM, this version matches the PPC. However I would question
how useful a self decompressing image is with a boot loader which does
decompression, so I think this is more useful. I also feel it matches
the descrition in the help text ("Compressed kernel image") better.
Signed-off-by: Thomas Betker <thomas.betker@5etech.eu> Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Stuart Menefy [Fri, 30 Nov 2007 09:16:23 +0000 (18:16 +0900)]
sh: get_user fixes and nommu consolidation.
When a get_user(to, from++) is called the pointer increment is performed
after its first usage, in the specific after the __add_ok invokation.
This causes a wrong get_user return value, putting a wrong character
in the destination variable. This patch solves the problem using a new
temporary pointer.
Additionally this reworks the use of the register banks, allowing for
consolidation between the MMU and nommu implementations.
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com> Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com> Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Stuart Menefy [Fri, 30 Nov 2007 08:06:36 +0000 (17:06 +0900)]
sh: Preparation for uncached jumps through PMB.
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Stuart Menefy [Fri, 30 Nov 2007 07:12:36 +0000 (16:12 +0900)]
sh: GUSA atomic rollback support.
This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Wed, 28 Nov 2007 10:14:23 +0000 (19:14 +0900)]
rtc: rtc-sh: Split out the CPU defs to asm/cpu/.
With all of the different CPU types this was getting a but unwieldly.
Since sh64 is now integrated, we don't have to worry about multiple
architectures caring about the header definitions.
Split out the defs for each asm/cpu/ to make rtc-sh slightly less
visually offensive.
Paul Mundt [Wed, 28 Nov 2007 06:56:27 +0000 (15:56 +0900)]
sh: CCR1->CCR renaming for SH-2 parts.
Avoid namespace collision with a CCR1 definition. The general
SH code always expects CCR anyways, so there's no point in keeping
the CCR1 naming around.
Fixes up synclink collisions:
drivers/char/pcmcia/synclink_cs.c:283:1: warning: "CCR1" redefined
In file included from include/asm/cache.h:13,
from include/asm/processor_32.h:15,
from include/asm/processor.h:60,
from include/linux/prefetch.h:14,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/char/pcmcia/synclink_cs.c:38:
include/asm/cpu/cache.h:21:1: warning: this is the location of the previous definition
Reported-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Stuart Menefy [Mon, 26 Nov 2007 12:29:09 +0000 (21:29 +0900)]
sh: Provide a 29/32-bit physical hint for bootloaders.
Shoves a magic word in to the empty_zero_page section for the
bootloader to work out whether to start the kernel in 29-bit
or 32-bit mode.
[ Renesas CPUs already take care of the initial PMB mappings entirely
in hardware and decide on 29-bit/32-bit physical depending on which
pin powered up the CPU, so this is mostly for ST parts. -- PFM ].
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Mon, 26 Nov 2007 10:54:02 +0000 (19:54 +0900)]
sh: Add SH7263 CPU support.
This adds support for the SH7263 (SH-2A) CPU.
This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.
Paul Mundt [Tue, 20 Nov 2007 06:16:25 +0000 (15:16 +0900)]
sh: Merge sh and sh64 module.c.
This is trivial, in that they're both effectively the same for the base
relocations anyways. SH-5 doesn't need the unaligned bits, and has a
few extra relocations, which are never hit on non-SH5 parts.
projects / linux-beck.git / log