Daniel Mack [Mon, 2 Jun 2014 11:32:46 +0000 (13:32 +0200)]
of: of_mdio: export symbol of_mdiobus_link_phydev
Make of_mdiobus_link_phydev externally available.
This fixes CONFIG_OF_MDIO=m.
Signed-off-by: Daniel Mack <zonque@gmail.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 86f6cf41272 ("net: of_mdio: add of_mdiobus_link_phydev()") Signed-off-by: David S. Miller <davem@davemloft.net>
Daniel Mack [Mon, 2 Jun 2014 11:32:45 +0000 (13:32 +0200)]
net: of_mdio: use int type for address variable
Use int rather than u32 to fix the following warning:
drivers/of/of_mdio.c:147 of_mdiobus_register() warn: unsigned 'addr' is
never less than zero.
Signed-off-by: Daniel Mack <zonque@gmail.com> Fixes: 8f8382888cba ("net: of_mdio: factor out code to parse a phy's 'reg' property") Signed-off-by: David S. Miller <davem@davemloft.net>
Daniel Mack [Sat, 24 May 2014 07:34:27 +0000 (09:34 +0200)]
net: of_mdio: don't store the length of a property if we don't need to
of_get_property() can be called with NULL as 2nd argument if the caller
is not interested in the length of a property. Use that here so we can
get rid of a variable.
Signed-off-by: Daniel Mack <zonque@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Daniel Mack [Sat, 24 May 2014 07:34:26 +0000 (09:34 +0200)]
net: of_mdio: add of_mdiobus_link_phydev()
Add a function to walk the list of subnodes of a mdio bus and look for
a node that matches the phy's address with its 'reg' property. If found,
set the of_node pointer for the phy. This allows auto-probed pyh
devices to be augmented by information passed in via DT.
Signed-off-by: Daniel Mack <zonque@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Daniel Mack [Sat, 24 May 2014 07:34:25 +0000 (09:34 +0200)]
net: of_mdio: factor out code to parse a phy's 'reg' property
Factor out some logic into of_mdio_parse_addr() so it can be reused
later. While at it, use of_property_read_u32() rather than open-coding
the same logic again.
Signed-off-by: Daniel Mack <zonque@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
of: mdio: fix compile warning in of_mdiobus_register_phy()
Commit de906af1 (net: phy: make of_set_phy_supported work with genphy driver)
removed the last user of variable 'max_speed' in function
of_mdiobus_register_phy(), leading to compile warning "unused variable
‘max_speed’ [-Wunused-variable]". Thus remove it.
Signed-off-by: Christian Engelmayer <cengelma@gmx.at> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Sascha Hauer [Wed, 21 May 2014 13:29:45 +0000 (15:29 +0200)]
net: phy: make of_set_phy_supported work with genphy driver
of_set_phy_supported allows overwiting hardware capabilities of
a phy with values from the devicetree. of_set_phy_supported is
called right after phy_device_register in the assumption that
phy_probe is called from phy_device_register and the features
of the phy are already initialized. For the genphy driver this
is not true, here phy_probe is called later during phy_connect
time. phy_probe will then overwrite all settings done from
of_set_phy_supported
Fix this by moving of_set_phy_supported to the core phy code
and calling it from phy_probe.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
Florian Fainelli [Thu, 22 May 2014 16:47:50 +0000 (09:47 -0700)]
of: mdio: remove of_phy_connect_fixed_link
All in-tree drivers have been converted to use the new pair of
functions: of_is_fixed_phy_link() plus of_phy_register_fixed_link(), we
can now safely remove of_phy_connect_fixed_link.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Thomas Petazzoni [Fri, 16 May 2014 14:14:05 +0000 (16:14 +0200)]
of: provide a binding for fixed link PHYs
Some Ethernet MACs have a "fixed link", and are not connected to a
normal MDIO-managed PHY device. For those situations, a Device Tree
binding allows to describe a "fixed link" using a special PHY node.
This patch adds:
* A documentation for the fixed PHY Device Tree binding.
* An of_phy_is_fixed_link() function that an Ethernet driver can call
on its PHY phandle to find out whether it's a fixed link PHY or
not. It should typically be used to know if
of_phy_register_fixed_link() should be called.
* An of_phy_register_fixed_link() function that instantiates the
fixed PHY into the PHY subsystem, so that when the driver calls
of_phy_connect(), the PHY device associated to the OF node will be
found.
These two additional functions also support the old fixed-link Device
Tree binding used on PowerPC platforms, so that ultimately, the
network device drivers for those platforms could be converted to use
of_phy_is_fixed_link() and of_phy_register_fixed_link() instead of
of_phy_connect_fixed_link(), while keeping compatibility with their
respective Device Tree bindings.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Jason Gunthorpe [Wed, 19 Mar 2014 22:15:24 +0000 (16:15 -0600)]
of_mdio: Allow the DT to specify the phy ID and avoid autoprobing
This makes the generic of_mdiobus_register parse the DT compatible string for
the pattern ethernet-phy-idAAAA.BBBB. If present it should be a value that
matches the phy-id register normally readable through MDIO.
When the ID is given the phy autoprobing is defeated and the phy is
created directly.
This is necessary to support phy's that cannot be autoprobed when
of_mdiobus_register is called. Specifically, my case has the phy in reset at
of_mdiobus_register, the reset is only released once the ethernet driver
starts, before it attaches to the phy.
Tested on ARM Kirkwood with phy id 0x01410e90 (Marvell 88E1318)
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Shawn Guo [Fri, 27 Jun 2014 08:32:46 +0000 (16:32 +0800)]
ENGR00318063-14: ARM: imx6sx: set pll2_bus as the default parent of QSPI clock
We already know that pll2_bus is the best parent of QSPI clock. Let's
set it up in clock initialization as the default, so that we can save
those implicit parent switching and rate changing calls from clock
framework.
shawn.guo: cherry-pick commit ecef6a715f1a from imx_3.10.y
Shawn Guo [Fri, 27 Jun 2014 04:39:54 +0000 (12:39 +0800)]
ENGR00318063-13: ARM: imx: do not reparent during clk_set_rate
Without flag CLK_SET_RATE_NO_REPARENT, during clk_set_rate call, clock
framework will spontaneously switch parent if there is another parent
clock which can provide a better rate. Such implicit clock reparent
sometimes results in unexpected clock tree topology change. Also, with
flag CLK_SET_PARENT_GATE in place, the clk_set_rate() can fail due to
this spontaneous clock switch. So let's stop clock framework from doing
this spontaneous reparent by adding flag CLK_SET_RATE_NO_REPARENT for
mux clocks.
While at it, adds the missing CLK_SET_PARENT_GATE flag for the fixup mux
clock also.
shawn.guo: cherry-pick commit f99c1687c820 from imx_3.10.y
ENGR00318063-12: ARM: imx6: enable clocks only after all parent and rate are initialized
This is a forward porting of commit ebf625e1a496 (ENGR00318063-12: ARM:
imx6: enable clocks only after all parent and rate are initialized) from
imx_3.10.y to imx_3.14.y.
Shawn Guo [Thu, 5 Jun 2014 08:54:31 +0000 (16:54 +0800)]
ENGR00318063-9: clk: do not allow parent switching with another mux being child
When switching parent clock with another basic mux clock being its
child, a glitch might be generated and propagated to downstream clocks
through this child mux.
The patch adds a flag CLK_IS_BASIC_MUX to identify the basic mux clocks,
and prohibit the parent switching when the clock itself is the parent of
any basic mux clock. With this check, the parent switching of a clock
has to happen before the child mux switches to this clock path.
shawn.guo: cherry-pick commit 8df4202f6a46 from imx_3.10.y
ENGR00318063-7: ARM: imx6q: mmdc_ch_axi clock should be non-gateable
Per the updated CCM chapter, there is no gate for clock mmdc_ch1_axi.
And there is a gate for mmdc_ch0_axi, but the gate also controls FABRIC
clock, which means the gate cannot be gated anyway. That said,
implementing these two clocks as gate does not make too much sense.
Remove these two gate clocks by pointing IMX6QDL_CLK_MMDC_CH0_AXI and
IMX6QDL_CLK_MMDC_CH1_AXI to the dividers.
Shawn Guo [Wed, 28 May 2014 07:46:44 +0000 (15:46 +0800)]
ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks
The i.MX6 Reference Manual requires PLLs to be powered down before
changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and
audio/video dividers to enforce the check at clock core level. So any
clk_set_rate() call from clients on these clocks will fail if the clocks
are not disabled and unprepared.
shawn.guo: cherry-pick commit 763c47cb3684 from imx_3.10.y
ENGR00329450 ARM: imx: set CLK_SET_RATE_GATE for gate and divider clocks
A recent QSPI boot failure (5% possibility) on i.MX6SX reminds us that
the peripheral clocks are still missing the check, rate cannot be
changed when the clock is enabled due to the glitchy multiplexers.
Commit a63839445ad3 (ENGR00325423: ARM: imx: pllv3 can only be
configured when it's powered off) adds the check for PLL clocks but
misses the peripheral clocks. The patch uses the help from clock
framework to check the condition with flag CLK_SET_RATE_GATE.
We adds flag CLK_SET_RATE_GATE for i.MX gate and divider clocks on
which the client drivers usually make clk_set_rate() call, so that the
call will fail when clock is still on instead of standing the risk of
running into glitch issue.
shawn.guo: cherry-pick commit 6487168bc783 from imx_3.10.y
Shawn Guo [Mon, 26 May 2014 08:37:25 +0000 (16:37 +0800)]
ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy mux clocks
The mux clocks found on imx6 SoCs are all glitchy ones except
pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When
switching parent clock of a glitchy mux without gating, a glitch could
be generated and propagated into the downstream divider, and hence locks
up the divider and results in no clock output.
To avoid the situation, the parent switching should happen only when
the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks,
so that clock core will make that check during clk_set_parent() call.
Since glitchless clocks do not need this flag, we create
imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel
and periph2_clk_sel are registered by imx_clk_busy_mux() which does not
set this flag anyway, so they need no change.
shawn.guo: cherry-pick commit 10bae51219b3 from imx_3.10.y
The current imx6sx clock driver combines two mux clocks ocram_alt_sel
and ocram_sel into one, while ocram_alt_sel is a glitchy mux and
ocram_sel is a glitchless one. Fix it to match the clock tree in
Reference Manual.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy ocram_alt_sel only when ocram_sel selects the
other path, i.e. periph. Otherwise, a glitch could be generated on
ocram_alt_sel and get propagated into the divider ocram_podf. In that
case, ocram_podf gets locked up and ocram clock has no output.
shawn.guo: cherry-pick commit a3b6793d21d9 from imx_3.10.y
The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one. Fix it to match the clock tree in Reference Manual.
shawn.guo: cherry-pick commit 973abca21604 from imx_3.10.y
Let's say clock A and B are two gate clocks that share the same register
bit in hardware. Therefore they are registered as shared gate clocks
with imx_clk_gate2_shared().
In a scenario that only clock A is enabled by clk_enable(A) while B is
not used, the shared gate will be unexpectedly disabled in hardware.
It happens because clk_enable(A) increments the share_count from 0 to 1,
while clock B is unused to clock core, and therefore the core function
will just disable B by calling clk->ops->disable() directly. The
consequence of that call is share_count is decremented to 0 and the gate
is disabled in hardware, even though clock A is still in use.
The patch fixes the issue by initializing the share_count per hardware
state and returns enable state per share_count from .is_enabled() hook,
in case it's a shared gate.
While at it, add a check in clk_gate2_disable() to ensure it's never
called with a zero share_count.
The ocotp also plays as a fuse device beside the system controller we
already have in device tree. Let's add a device node for the fuse
device for imx6qdl and imx6sl.
While at it, the patch also drops "fsl,imx6q-ocotp" and
"fsl,imx6sl-ocotp" from system controller compatible string, since
it's not used, and use node name ocotp-ctrl and ocotp-fuse for system
controller and fuse device respectively.
shawn.guo: cherry-pick commit 1a8c2aef633c from imx_3.10.y, and add the
same change for imx6sx.
Jason Liu [Tue, 5 Nov 2013 04:03:18 +0000 (12:03 +0800)]
ARM: i.MX6: add more chip revision support
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
ENGR00277955-2 rtc: rtc-snvs: support wakeup system from freeze mode
To support wakeup system from freeze mode of suspend,
device's irq can NOT be disabled during devices suspend,
so we need to add IRQF_NO_SUSPEND flag to irqflags.
ENGR00277955-1 keyboard: gpio_keys: support wakeup system from freeze mode
To support wakeup system from freeze mode of suspend,
device's irq can NOT be disabled during devices suspend,
so we need to add IRQF_NO_SUSPEND flag to irqflags.
Luwei Zhou [Fri, 20 Dec 2013 02:23:39 +0000 (10:23 +0800)]
ENGR00281813 input: mma8450: evbug module will keep print message.
evbug will open the mma8450 on i.MX6SL_EVK and mma8450 will work in 2G mode by default.
That is the reason why mma8450 logs will be printed out. The main changes is below:
* Remove the open(), close() hook out of the drivers. The open() and close()
hook in input framwork is defined as void type. It isn't strictly safe in
logic when some error happends. So remove them out.
* Modify the mma8450 to standby mode by default. It will be more power saving
and there would be no log printing out after booting up.
* Provide the sys interface to modify the mma8450 work modes. Then the higher
layer can modify the the mma8450 work mode via the interface. It would be
much safer.There would be a sclaemode interface in the folder of
/sys/devices/soc0/soc.1/2100000.aips-bus/21a0000.i2c/i2c-0/0-001c/scalemode
User can use cat to read the current scalemode and echo to write. The mode
is defined as: MODE_STANDBY: 0 MODE_2G:1 MODE_4G:2 MODE_8G:3
* Add mutex to protect and some error handling.
ENGR00277864 input: mma8450: Add chip id check in probe
Add chip ID check in probe function. The mma8450 is
on the E-INK daughter board. When the daughter board
is not pluged, there would be polling error log
continuously. Add the check to avoid this.
ENGR00321358-2 dts: imx6sx: change m_can message ram to a small size
We met an issue that access the 0x2600 offset of message ram
does not work although the mx6sx spec claims a 16KB size.
The reason is still unkown.
Change the RAM size to a small size to use the first 2K
to avoid such issue.
Dong Aisheng [Thu, 19 Jun 2014 10:49:37 +0000 (18:49 +0800)]
ENGR00319455-1 can: m_can: add Bosch M_CAN controller support
The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller.
For TX, only one dedicated tx buffer is used for sending data.
For RX, RXFIFO 0 is used for receiving data to avoid overflow.
Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO.
Due to the message ram can be shared by multi m_can instances
and the fifo element is configurable which is SoC dependant,
the design is to parse the message ram related configuration data from device
tree rather than hardcode define it in driver which can make the message
ram using fully transparently to M_CAN controller driver,
then we can gain better driver maintainability and future features upgrade.
M_CAN also supports CANFD protocol features like data payload up to 64 bytes
and bitrate switch at runtime, however, this patch still does not add the
support for these features.
Dong Aisheng [Mon, 24 Feb 2014 06:25:12 +0000 (14:25 +0800)]
ENGR00300439-5 can: flexcan: parse stop mode control bits from device tree
Starting from IMX6, the flexcan stop mode control bits is SoC specific,
move it out of IP driver and parse it from devicetree.
It's good from maintain perspective and can avoid adding too many SoC
specifi bits in driver but with no IP changes when the IMX SoC series
keep growing.
ENGR00258885 flexcan: fix errata ERR005829 that MB may fail to be sent
This is an issue from IC errata ERR005829 which is described as follows:
----------------------------------------------------------
FlexCAN does not transmit a message that is enabled to be transmitted
in a specific moment during the arbitration process. The following
conditions are necessary to have the issue.
- Only one MB is configured to be transmitted
- The write which enables the MB to be transmitted (write on Control status
word) happens during a specific clock during the arbitration process.
After this arbitration process occurs, the bus goes to Idle state and no
new message is received on bus.
For example:
1) MB13 is deactivated on RxIntermission (write 0x0 on CODE field from Control
Status word) - First write on CODE
2) Reconfigure the ID and data fields
3) Enable the MB13 to be transmitted on BusIdle (write 0xC on Code
field) - Second write on code
4) CAN bus keeps in Idle state
5) No write on Control status from any MB happens.
During the second write on code (step 3), the write must happen one clock
before the current MB13 is to be scanned by arbitration process.
In this case, it does not detect the new code (0xC) and no new arbitration is
scheduled.
The suggested workaround which is implemented in this patch is:
The workaround consists of executing two extra steps:
6. Reserve the first valid mailbox as an inactive mailbox (CODE=0b1000).
If RX FIFO is disabled, this mailbox must be MB0. Otherwise, the first
valid mailbox can be found by using table "RX FIFO filters" on FlexCAN3 chapter.
7. Write twice INACTIVE code (0b1000) into the first valid mailbox.
Note: The first mailbox cannot be used for reception or transmission process.
-------------------------------------------------------------
Note: Although the currently flexcan driver does not have the step 1 to run,
it's also possible to meet this issue in theory because we can not predict
when the arbitration is scheduled.
With a modified can-utils/canfdttest tool simulating Pingpong test, we were
able to reproduce this issue after running a about one day.
After applying this patch, we ran six days and did not see the issue happen
again on two mx6q sabrelite boards.
Note: with a few minors change for new kernel and change errata id from
ERR005641 to ERR005829 which is the open one in freescale website.
Dong Aisheng [Wed, 6 Nov 2013 11:10:28 +0000 (19:10 +0800)]
ENGR00286724-8 can: flexcan: add self wakeup support
If wakeup is enabled, enter stop mode, else enter disabled mode.
Self wake can only work on stop mode.
For imx6q, the stop request has to be mannually assert on
IOMUX GPR13[28:29] register, we use syscon to control that bit.
Antoine Ténart [Wed, 30 Jul 2014 18:13:56 +0000 (20:13 +0200)]
ata: libahci_platform: move port_map parameters into the AHCI structure
This patch moves force_port_map and mask_port_map into the
ahci_host_priv structure. This allows to modify them into the AHCI
framework. This is needed by the new dt bindings representing ports as
the port_map mask is computed automatically.
Parameters modifying force_port_map, mask_port_map and flags have been
removed from the ahci_platform_init_host() function, and inputs in the
ahci_host_priv structure are now directly filed.
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 725c7b570fda4207e465ff8856c2c12c2645a685)
ahci_xgene: Use correct OOB tunning parameters for APM X-Gene SoC AHCI SATA Host controller driver.
APM X-Gene SoC AHCI SATA Host controller driver requires
some correction of Phy Control OOB timing for the
COMINIT/COMWAKE parameters to correctly interoperate with
different kinds of disks.
Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 0185b1b787962db38fdf74e1cab9b7a2619490a1)
ahci_xgene: Fix the watermark threshold for the APM X-Gene SATA host controller driver.
As per SATA IO specification, when Host sends HOLD, the device takes
about 20DW latency to reply to HOLDA. In some case, device doesn't
response to HOLDA over 20DW and causes FIFO goes into over flow
condition. Due to this condition, device enumerations fails with
those devices. This patch adjust the watermark FIFO by increasing
the FIFO depth from 0x16(default) to 0x30 to address this issue.
Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit aeae4dcac5a91de9546c42a3be09c96479bfc3ff)
Mikko Perttunen [Fri, 18 Jul 2014 07:12:30 +0000 (10:12 +0300)]
ata: Add support for the Tegra124 SATA controller
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit ccfde50810ae916564765a2f8ee6d7163b025594)
Mikko Perttunen [Wed, 16 Jul 2014 08:54:21 +0000 (11:54 +0300)]
ata: ahci_platform: Increase AHCI_MAX_CLKS to 4
The Tegra124 SATA controller requires 4 clocks. Increase this constant
to be able to use them all.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 0e38699387fd2fd433618bb67612f3aae676fbae)
libata: EH should handle AMNF error condition as a media error
libata-eh.c should handle AMNF error condition (error byte bit 0,
usually code 0x01) in libata-eh.c along with UNC as a media error so
SCSI stack can handle it properly (translation code 0x01 is already
present in libata-scsi.c) but was never passed down due to lack of
handling in EH.
While using linux-based machine (AMD 6550M-based notebook, PCI IDs for the
controller are 1022:7801 subsys 1025:059d) and ddrescue to salvage data
from failing hard drive (WD7500BPVT 2.5" 750G SATA2), I've found that pure
AMNF 0x01 error code generates generic "device error" that is retried
several times by SCSI stack instead of "media error" that is passed up to
software.
So we may assume deprecated AMNF error code is surely not dead yet, and
it's better for it to be handled properly. As we may see it is used by
modern enough devices, and used properly: drive returned AMNF only when IDs
for track cannot be read completely due to dying head or positioning,
otherwise it returned UNC(orrectables).
Not handling it causes wrong generic error code ("device error") reporting
down the stack, can damage failing drives further because of excessive
retries, and slows salvaging down a lot. Also, there is handling code in
libata-scsi.c for 0x01 AMNF error already.
https://bugzilla.kernel.org/show_bug.cgi?id=80031
tj: Shortened $SUBJ and moved its content to the first paragraph.
ahci_xgene: fix the dma state machine lockup for the IDENTIFY DEVICE PIO mode command.
This patch fixes the dma state machine lockup due to the processing
of IDENTIFY DEVICE PIO mode command. The X-Gene AHCI controller
has an errata in which it cannot clear the BSY bit after the PIO setup
FIS. The dma state machine enters CMFatalErrorUpdate state and locks
up. This patch also removes the dma restart workaround from the read_id
function as the read_id function is only called by libata layer for
ATA_INTERNAL commands. But for some cases eg: PORT MULTIPLIER
and udev, the framework will enumerate using SCSI commands and it will
not call read_id function.
Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 2a0bdff6b958d1b2523d2754b6cd5e0ea4053016)
Russell King [Tue, 24 Jun 2014 10:19:47 +0000 (11:19 +0100)]
ata: ahci_imx: add disable for spread-spectrum
Spread-spectrum doesn't work with Cubox-i hardware, so we have to
disable this feature. Add a DT property so that platforms can
indicate that this feature should not be enabled.
Having it as a negative property keeps existing DT files working.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit a6e726244c78e04d0af754c625036be8f92a9afd)
Russell King [Mon, 23 Jun 2014 11:59:08 +0000 (12:59 +0100)]
ata: ahci_imx: warn when disabling ahci link
When the AHCI link is disabled, it can't be re-enabled except by
resetting the entire SoC. Rather than doing this silently print
some kernel messages to inform the user, along with how to avoid
this.
tj: Put a long printf format string on a single line.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit f118ae5901172dacc4f272acf5eccfba06e8d221)
The reason is that the SATA controller has no working clock at this
point, and thus ahci_enable_ahci() fails to enable the controller. In
case that there is no SATA disk attached, the imx_sata_disable() gets
called in ahci_imx_error_handler(), and both sata_clk and sata_ref_clk
will be disabled there. Because all the imx_sata_enable() calls
afterward will return immediately due to imxpriv->no_device check, the
SATA controller working clock sata_clk will never get any chance to be
enabled again.
This is a regression caused by commit 90870d79d4f2 (ahci-imx: Port to
library-ised ahci_platform). Before the commit, only sata_ref_clk is
managed by the driver in enable/disable function. But after the commit,
all the clocks are enabled/disabled in a row by ahci platform helpers
ahci_platform_enable[disable]_clks. Since ahb_clk is a bus clock which
does not have gate at all, and i.MX low-power hardware module already
manages sata_clk across suspend/resume cycle, the only clock that needs
to be managed by software is sata_ref_clk.
So instead of using ahci_platform_enable[disable]_clks to manage all
the clocks in a row from imx_sata_enable[disable], we should manage
only sata_ref_clk in there.
Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: 90870d79d4f2 (ahci-imx: Port to library-ised ahci_platform) Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
(cherry picked from commit e6dd42a917e62d916c6e513dbf87a4dec8cf3a1c)
ahci: Check and set 64-bit DMA mask for platform AHCI driver
The current platform AHCI driver does not set the dma_mask correctly
for 64-bit DMA capable AHCI controller. This patch checks the AHCI
capability bit and set the dma_mask and coherent_dma_mask accordingly.
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit cc7a9e27562cd78a1dc885504086fab24addce40)
Mikko Perttunen [Tue, 17 Jun 2014 12:07:55 +0000 (15:07 +0300)]
libahci_platform: Fail when PHY required but PHY support disabled
ahci_platform_get_resources handles resource management for
platform AHCI drivers, including getting a possible PHY
from the device tree. Since not all drivers need a PHY, it
ignores -ENODEV and -ENOSYS from devm_get_phy. However, when
the PHY subsystem is mistakenly disabled, -ENOSYS can be
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a "phys"
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit acbd573354bb7b7b7a3891018a39f4b3976b0c43)
Paul Bolle [Wed, 21 May 2014 19:35:37 +0000 (21:35 +0200)]
sata_fsl: remove check for CONFIG_MPC8315_DS
A check for CONFIG_MPC8315_DS was added in v2.6.24. But the related
Kconfig symbol was never added to the tree. So the code behind this
check has effectively been dead for over six years. Remove it.
Shawn Guo [Sat, 17 May 2014 12:46:01 +0000 (20:46 +0800)]
ahci: imx: PLL clock needs 100us to settle down
The commit e783c51 (ahci: imx: software workaround for phy reset issue
in resume) calls imx_sata_phy_reset() to reset phy immediately after
SATA MPLL is enabled. It seems working fine mostly, but fails in some
case as below.
...
ahci-imx 2200000.sata: failed to reset phy: -110
ahci-imx: probe of 2200000.sata failed with error -110
After talking to the designer, we learnt that when enabling i.MX6Q SATA
MPLL, we need to wait 100us for it to settle down for safety. Add this
required delay to fix above failure.
Kefeng Wang [Wed, 14 May 2014 06:13:42 +0000 (14:13 +0800)]
ahci: add support for Hisilicon sata
The hip04 SoC of hisilicon has an AHCI compliant SATA controller,
and it is compliant with the ahci 1.3 and sata 3.0 specification.
There is a wrong bit in HOST_CAP of hip04 sata controller, which
enable unsupported feature of FBS, use AHCI_HFLAG_NO_FBS hflag to
disable it.
Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit a1a205df6ee224f62c6d21cedebcb723db17fe0d)
Kefeng Wang [Wed, 14 May 2014 06:13:41 +0000 (14:13 +0800)]
libahci_platform: add host_flags parameter in ahci_platform_init_host()
Add a dynamic host_flags argument to make ahci_platform_init_host more flexible,
then remove the AHCI_HFLAGS(...) argument from some driver's ata_port_info,
and pass that in as the new argument.
Cc: Hans de Geode <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit f9f36917903b57c571b1ddcfc6bc794ca4dd8232)
Thomas Petazzoni [Tue, 15 Apr 2014 15:00:03 +0000 (17:00 +0200)]
ata: ahci_mvebu: new driver for Marvell Armada 380 AHCI interfaces
The Marvell Armada 380 SoC includes two AHCI compatible
interfaces. However, like all DMA-capable Marvell interface, they
require special handling to configure MBus windows. Therefore, this
commit adds a new ahci_mvebu driver, which relies on the
libahci_platform.c code recently introduced.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit a3464ed2f14d19ba923930f7c0c284499d64eb5b)
Thomas Petazzoni [Tue, 15 Apr 2014 15:00:02 +0000 (17:00 +0200)]
Documentation: dt-bindings: reformat and order list of ahci-platform compatibles
The ahci-platform.txt Device Tree binding documentation is gaining a
growing number of compatible strings, and it will gain one more with
the addition of the Marvell Armada 380 AHCI support. It is therefore
time to reformat this list into a proper bullet list, and more
importantly order it alphabetically;
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 5799d6d4cf86c11503aee909a1ec555453c7f22a)
Shawn Guo [Sun, 4 May 2014 13:48:06 +0000 (21:48 +0800)]
ahci: imx: software workaround for phy reset issue in resume
When suspending imx6q systems which have rootfs on SATA, the following
error will likely be seen in resume. The SATA link will fail to come
up, and it results in an unusable system across the suspend/resume
cycle.
$ echo mem > /sys/power/state
PM: Syncing filesystems ... done.
PM: Preparing system for mem sleep
Freezing user space processes ... (elapsed 0.002 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
PM: Entering mem sleep
sd 0:0:0:0: [sda] Synchronizing SCSI cache
sd 0:0:0:0: [sda] Stopping disk
PM: suspend of devices complete after 61.914 msecs
PM: suspend devices took 0.070 seconds
PM: late suspend of devices complete after 4.906 msecs
PM: noirq suspend of devices complete after 4.521 msecs
Disabling non-boot CPUs ...
CPU1: shutdown
CPU2: shutdown
CPU3: shutdown
Enabling non-boot CPUs ...
CPU1: Booted secondary processor
CPU1 is up
CPU2: Booted secondary processor
CPU2 is up
CPU3: Booted secondary processor
CPU3 is up
PM: noirq resume of devices complete after 10.486 msecs
PM: early resume of devices complete after 4.679 msecs
sd 0:0:0:0: [sda] Starting disk
PM: resume of devices complete after 22.674 msecs
PM: resume devices took 0.030 seconds
PM: Finishing wakeup.
Restarting tasks ... done.
$ ata1: SATA link down (SStatus 1 SControl 300)
ata1: SATA link down (SStatus 1 SControl 300)
ata1: limiting SATA link speed to 1.5 Gbps
ata1: SATA link down (SStatus 1 SControl 310)
ata1.00: disabled
ata1: exception Emask 0x10 SAct 0x0 SErr 0x4040000 action 0xe frozen t4
ata1: irq_stat 0x00000040, connection status changed
ata1: SError: { CommWake DevExch }
ata1: hard resetting link
sd 0:0:0:0: rejecting I/O to offline device
sd 0:0:0:0: killing request
sd 0:0:0:0: rejecting I/O to offline device
Aborting journal on device sda2-8.
sd 0:0:0:0: rejecting I/O to offline device
EXT4-fs warning (device sda2): ext4_end_bio:317: I/O error writing to inode 132577 (offset 0 size 0 starting block 26235)
Buffer I/O error on device sda2, logical block 10169
...
It's caused by a silicon issue that SATA phy does not get reset by
controller when coming back from LPM. The patch adds a software
workaround for this issue. It enforces a software reset on SATA phy
in imx_sata_enable() function, so that we can ensure SATA link will
come up properly in both power-on and resume.
The software reset is implemented by writing phy reset register through
the phy control register bus interface. Functions
imx_phy_reg_[addressing|write|read]() implement this bus interface, while
imx_sata_phy_reset() performs the actually reset operation.
Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit e783c51cce94521c10e599e991acdcfd9a996c4a)
Paul Bolle [Sun, 4 May 2014 11:50:29 +0000 (13:50 +0200)]
libata-sff: remove dead code
Ever since v2.6.19 the code contains a check for CONFIG_NO_ATA_LEGACY.
But that macro has never been defined. Apparently no one ran into
problems on platforms that do not support compatibility mode. So remove
this code that has been dead for over seven years.
Keith Busch [Thu, 1 May 2014 17:12:03 +0000 (11:12 -0600)]
ata: SATL compliance for Inquiry Product Revision
The SCSI-to-ATA Translation standard says to use data words 25 and 26
unless they are spaces. For devices that use these words in the firmware
field, they are generally more useful anyway.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit c49a6bf5eecd31f335df1a3700c92be1a824c6f0)
ahci: Ensure "MSI Revert to Single Message" mode is not enforced
The AHCI specification allows hardware to choose to revert to
single MSI mode when fewer messages are allocated than requested.
Yet, at least ICH10 chipset reverts to single MSI mode even when
enough messages are allocated in some cases (see below).
This update forces the driver to not rely on initialization of
multiple MSIs mode alone and always check if "MSI Revert to
Single Message" (MRSM) mode was enforced by the controller and
fallback to the single MSI mode in case it did.
That prevents a situation when the driver configured multiple
per-port IRQ handlers, but the controller sends all port's
interrupts to a single IRQ, which could easily screw up the
interrupt handling and lead to delays and possibly crashes.
The fix was tested on a 6-port controller that successfully
reverted to the single MSI mode:
00:1f.2 SATA controller: Intel Corporation 82801JI (ICH10 Family) SATA
AHCI Controller (prog-if 01 [AHCI 1.0])
Subsystem: Super Micro Computer Inc Device 10a7
Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 101
I/O ports at f110 [size=8]
I/O ports at f100 [size=4]
I/O ports at f0f0 [size=8]
I/O ports at f0e0 [size=4]
I/O ports at f020 [size=32]
Memory at fbf00000 (32-bit, non-prefetchable) [size=2K]
Capabilities: [80] MSI: Enable+ Count=1/16 Maskable- 64bit-
Capabilities: [70] Power Management version 3
Capabilities: [a8] SATA HBA v1.0
Capabilities: [b0] PCI Advanced Features
Kernel driver in use: ahci
With 6 ports just 8 MSI vectors should be enough, but the adapter
enforces the MRSM mode when less than 16 vectors are written to
the Multiple Messages Enable PCI register. I instigated MRSM mode
by forcing @nvec to 8 in ahci_init_interrupts().
Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Cc: linux-ide@vger.kernel.org Cc: stable@vger.kernel.org Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit ab0f9e78b97f5193dd38b3757b42b6fbded05fb7)
AHCI_XGENE is only applicable on ARM64 but it can also be enabled for
compile testing; however, AHCI_XGENE selects PHY_XGENE which has other
arch specific dependencies. This leads to the following warning when
enabling it on other archs for compile testing.
warning: (AHCI_XGENE) selects PHY_XGENE which has unmet direct
dependencies (HAS_IOMEM && OF && (ARM64 || COMPILE_TEST))
Selecting a config option which itself has dependencies can easily
lead to broken configurations. For now, let's just make AHCI_XGENE
depend on PHY_XGENE which has all the necessary dependencies already.
Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Loc Ho <lho@apm.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit 74c03eb63061c834893e7ebf8d298573bdccfd08)
Make pata_arasan_cf host driver depend on ARCH_SPEAR13XX config
option as ARASAN CompactFlash PATA support is specific to ST
SPEAr13xx SoCs and the driver to work requires suitable device
tree node (or platform device) to be defined. Additionally
allow the driver build if COMPILE_TEST config option is set.
ata: fix Calxeda Highbank SATA driver dependencies
Make sata_highbank host driver depend on ARCH_HIGHBANK config option
as Calxeda Highbank SATA support is specific to Calxeda Highbank
SoCs and the driver to work requires suitable device tree node to
be defined. Additionally allow the driver build if COMPILE_TEST
config option is set.
Cc: Mark Langsdorf <mark.langsdorf@calxeda.com> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 0b99f8648eb1814d787db3981ad93e6bc343b3f6)
Make sata_rcar host driver depend on ARCH_SHMOBILE config option as
Renesas R-Car SATA support is specific to Renesas SoCs and the driver
to work requires suitable device tree node (or platform device) to be
defined. Additionally allow the driver build if COMPILE_TEST config
option is set.
Cc: Simon Horman <horms@verge.net.au> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 7596d93d8dfa7a508ca52c7d9b7db763eb5b0715)
Platform changes needed to make DaVinci DA850 SATA AHCI support
fully functional are in the separate "ARM: davinci: da850: update
SATA AHCI support" commit.
Please note that this driver doesn't have the superfluous clock
control code as clock is already handled by the generic AHCI
platform library code.
Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit ae8723f8a9c8e804c2b906074d7d5f1265a385bb)
Paul Gortmaker [Tue, 21 Jan 2014 21:22:51 +0000 (16:22 -0500)]
ata: delete non-required instances of include <linux/init.h>
None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Cc: linux-ide@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 1bc18086231c130895b87ec049be8ddcdab552b8)
Looking at ST SPEAr1340 AHCI code (the only user of the deprecated
pdata->suspend and pdata->resume) it is obvious the we should return
after calling pdata->suspend() only if the function have returned
non-zero return value. The code has been broken since commit 1e70c2
("ata/ahci_platform: Add clock framework support"). Fix it.
Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 83b03fd67b9b3fa3795871169f3c08c35b3d6ea8)
Todd Brandt [Fri, 14 Mar 2014 20:52:54 +0000 (13:52 -0700)]
libata: async resume
Improve overall system resume time by making libata link recovery
actions asynchronous relative to other resume events.
Link resume operations are performed using the scsi_eh thread, so
commands, particularly the sd resume start/stop command, will be held
off until the device exits error handling. Libata already flushes eh
with ata_port_wait_eh() in the port teardown paths, so there are no
concerns with async operation colliding with the end-of-life of the
ata_port object. Also, libata-core is already careful to flush
in-flight pm operations before another round of pm starts on the given
ata_port.
Cc: Len Brown <len.brown@intel.com> Cc: Phillip Susi <psusi@ubuntu.com> Cc: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Todd Brandt <todd.e.brandt@linux.intel.com>
[djbw: rebase on cleanup patch, changelog wordsmithing] Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
(cherry picked from commit 200421a80f6e0a9e39d698944cc35cba103eb6ce)
projects / karo-tx-linux.git / log