ENGR00333303 dts: imx6sx-sdb-emmc: add emmc support on uSDHC4
The eMMC interface is shared with uSDHC4 BOOT card slot and the eMMC chip is
DNP by default. User needs burn the eMMC chip onto the board manually and
do hw rework to enable eMMC signals.
We create a new dts imx6sx-sdb-emmc.dts for easy eMMC test after doing hw rework.
Robby Cai [Fri, 19 Sep 2014 10:38:08 +0000 (18:38 +0800)]
ENGR00332319 lcdif: imx6sl: disable the pixel rate before call clk_set_rate
After the following commit is pushed, the lcdif framebuffer driver need
the adjustment. 93a9e3d0b88203cb523dd92e85590683d6a85fdf ENGR00318063-6:
ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks
CLK_SET_RATE_GATE flag means "must be gated across rate change".
PLL5 video is the parent clock of the pixel clock, and only used by it.
This patch gates the clock before call clk_set_rate() to meet the requirement.
ERROR (phandle_references): Reference to non-existent node or label "reg_sensor"
ERROR: Input tree has errors, aborting (use -f to force output)
make[1]: *** [arch/arm/boot/dts/imx6dl-cubox-i.dtb] Error 2
make[1]: *** Waiting for unfinished jobs....
DTC arch/arm/boot/dts/imx6dl-sabresd-enetirq.dtb
...
The label "reg_sensor" is defined in imx6qdl-sabresd.dts, not in
imx6dl.dtsi. The patch moves the epdc parts to imx6dl-sabresd.dts,
which also sounds better since EPDC module is available not on i.mx6q
but i.mx6dl.
Dong Aisheng [Fri, 10 Jan 2014 13:31:21 +0000 (21:31 +0800)]
ENGR00333129 dts: imx6qdl-sabreauto: use external vmmc for sd3 optionally
SD3.0 cards require power cycle the card during suspend/resume,
or the card re-enumeration after resume will fail to be identified
as UHS card since the card is already working on 1.8v mode and refuse
to ack the S18R request, thus, it will then work on normal high speed
mode instead.
We have to use external vmmc regulator to power cycle the card during
suspend/resume to reset card signal voltage to 3.3v frist for the later
1.8v voltage switch.
However, due to the sabreauto board limitation, we can not use external
regulator to powere off card by default since the card power is shared
with card detect pullup. Disabling the vmmc regulator will also shutdown
the cd pullup which causes incorrect illusion of card exist.
(e.g. plug out the card, mmc core wll think the card is exist since cd pin
is low but it never can find the card)
HW rework removing R695 and enable PAD internal pullup is needed to
fix this isssue.
User can manually open the mask of vmmc in dts to enable using external
regulator if your board has done the rework as said above.
Or by default we still do not power off card during suspend.
Dong Aisheng [Tue, 24 Jun 2014 09:25:03 +0000 (17:25 +0800)]
ENGR00319936-1 mmc: sdhci-esdhc-imx: do not enable wakeup by default
After adding mega fast support, the default enabled usdhc wakeup will block
M/F to gate off power domain.
To avoid this issue, we only claim wakeup capability and reply on user to enable
it via sysfs according to real needs.
The drawback of such change is that for SDIO WiFi Wakeup On Wireless feature,
User has to enable both uSDHC and WiFi WoW wakeup mannually to make
WoW work well.
BTW, due to the wakeup feature is controller itself, so we do not need to reply
on WiFi PM flags to enable it.
Dong Aisheng [Thu, 6 Mar 2014 08:04:19 +0000 (16:04 +0800)]
ENGR00332937-1 mmc: sdhci-esdhc-imx: add imx6sx support
The imx6sx usdhc is derived from imx6sl, the difference is minor.
imx6sx have the errata ESDHC_FLAG_ERR004536 fixed.
So introduce a new compatible string for imx6sx to distinguish them.
Dong Aisheng [Fri, 17 Jan 2014 02:23:22 +0000 (10:23 +0800)]
ENGR00295564 mmc: sdhci-esdhc-imx: no need busfreq for imx6qdl
The usdhc of i.MX6Q/DL can work well under low power mode without
request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
It can save power for i.MX6D/DL due to it saves a lot busfreq switch
cost as well as the CPU time runing on high bus freq after switch
during low power mode.
A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
Currently only i.MX6SL is using it.
Dong Aisheng [Tue, 31 Dec 2013 08:22:44 +0000 (16:22 +0800)]
ENGR00295184-1 mmc: sdhci: do not enable card detect interrupt for gpio cd type
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data transfer
which should not happen.
Dong Aisheng [Mon, 16 Dec 2013 06:42:14 +0000 (14:42 +0800)]
ENGR00292140 mmc: sdhci: fix possible sleep in atomic in sdio_irq enable function
The sdhci_runtime_pm_get API is able to sleep, so should not call it in
sdhci_enable_sdio_irq_nolock which is executed with spin_lock_irqsave in
sdhci_enable_sdio_irq.
Move it out of spin lock to fix this issue.
The max timeout counter for uSDHC is SDCLK x (1 << 28), not as standard
controller defined as TMCLK x (1 <<27).
Add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to handle it.
Dong Aisheng [Fri, 22 Nov 2013 12:34:38 +0000 (20:34 +0800)]
ENGR00289406-1 mmc: sdhci: add quirk for get max timeout counter
The max timeout counter of some SoCs like i.MX6 uSDHC may not be standard,
add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to get the correct max timeout
counter from platform specific code.
Then we can calculate the correct max_discard_to value.
Dong Aisheng [Fri, 15 Nov 2013 09:54:36 +0000 (17:54 +0800)]
ENGR00289279 mmc: sdhci: get runtime pm when sdio irq is enabled
SDIO cards may need clock to send the card interrupt to host.
Thus, we get runtime pm when sdio irq is enabled to prevent the clock
resource is released and put it when sdio irq is disabled.
The uSDHC has an ADMA Length Mismatch errata ERR004536 which may cause ADMA
work abnormally. The errata has already been fixed for i.MX6Q TO1.2
and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register.
Unfortunately this fix is not included in i.MX6SL.
So we disable ADMA for i.MX6SL and use SDMA instead.
Nimrod Andy [Fri, 19 Sep 2014 06:26:03 +0000 (14:26 +0800)]
net: fec: fix code identation
There have extra identation before .skb_copy_to_linear_data_offset(),
this patch just remove the identation.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Nicolin Chen [Tue, 25 Mar 2014 12:56:18 +0000 (20:56 +0800)]
ENGR00305648-1 ASoC: imx-sgtl5000: Support non-ssi cpu-dai
The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while
in fact it could be attached to other cpu-dais like SAI. Thus this patch
use a general code to support another cpu-dai. And meanwhile update the
devicetree for i.MX6 Series.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit cb5dfaf44d2fdbce4329c2e4762e8450c8cd3b3c)
Nicolin Chen [Tue, 24 Jun 2014 06:44:18 +0000 (14:44 +0800)]
ENGR00320241 ASoC: fsl_spdif: Complete the volatile register list
Not only SIS but also other read-only or write-only reigsters should be marked
as volatile register so as not to let regcache cache them. So this patch just
adds those missing registers.
Nicolin Chen [Thu, 15 May 2014 10:53:25 +0000 (18:53 +0800)]
ENGR00318773-10 ASoC: imx-audmux: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, AUDMUX needs to
save all the values of registers before the system suspend and restore them
after the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 3f3781143ba2800f7e3e46dbecc0c7a76d22a146)
Nicolin Chen [Thu, 15 May 2014 10:51:56 +0000 (18:51 +0800)]
ENGR00318773-9 ASoC: fsl_ssi: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SSI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 34c50abd9df28580b367070bc20b8bca6cd7655c)
Nicolin Chen [Wed, 14 May 2014 10:54:27 +0000 (18:54 +0800)]
ENGR00318773-8 ASoC: fsl_spdif: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SPDIF needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit fd7d2c1a137c1b9d7adb58aaf06b90938172b964)
Nicolin Chen [Mon, 12 May 2014 12:00:48 +0000 (20:00 +0800)]
ENGR00318773-7 ASoC: fsl_esai: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ESAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit fc69de0b0cc1d9a85ad7f7363da6dec02945964a)
Nicolin Chen [Mon, 12 May 2014 05:47:52 +0000 (13:47 +0800)]
ENGR00318773-6 ASoC: fsl_sai: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 88efde0cec71d7d70948eeaf1d22ab52b8bc8f2d)
Nicolin Chen [Thu, 17 Oct 2013 10:24:29 +0000 (18:24 +0800)]
ENGR00283079-1 ASoC: fsl: Implement different DMA buffer sizes
Each CPU DAI driver has its own defined DMA buffer size, so this patch just
drops the original one that uses a fixed size for all drivers and implements
a different DMA buffer size to each driver.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
(cherry picked from commit d2589c6bcdfbcac420999e15d36ecd48a7df2742)
Shengjiu Wang [Fri, 9 Aug 2013 06:45:51 +0000 (14:45 +0800)]
ENGR00274585-9 ASoC: change error message to debug message
This error message is not actual error, which is a warning. When using
FE/BE, if there is widget which is used by playback and capture route, then
this message will be printed.
Shengjiu Wang [Wed, 2 Jul 2014 09:24:45 +0000 (17:24 +0800)]
ENGR00320849-1 ASoC: cs4xx8: fix the setting of Functional mode
Failed case:
arecord -Dhw:0,1 -f S16_LE -r 96000 -c 2 -traw | aplay -Dhw:0,0 -f
S16_LE -r 96000 -c 2 -traw.
There is no sound when use this case.The reason is that the setting
of Functional mode is not correct.
ENGR00320678 ASoC: cs42xx8: Revert the DAPM routes to the old one
The upstream version of DAPM routes results record noise issue due to its
inappropriate power-up sequence. So we provisionally revert this change
to the old stable one, and figure out why the sequence has problem later.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 3cda4b6d88aa7b40ac22652df92fa449063bc35a)
Dylan Reid [Fri, 24 Jan 2014 23:40:39 +0000 (15:40 -0800)]
regmap: cache: Handle stride > 1 in sync_block_raw_flush
regcache_sync_block_raw_flush takes the address of the base register
and the address of one past the last register to write to. "count" is
the number of registers in the range, not the number of bytes, it
should be (end addr - start addr) / stride. Without accounting for
strides greater than one, registers past the end might be synced or
the writeable_reg callback at the beginning of _regmap_raw_write will
fail and nothing will be written.
Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 78ba73eecd2256790926859849801c0446766c0a) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Nicolin Chen [Mon, 12 May 2014 12:12:05 +0000 (20:12 +0800)]
ASoC: pcm: Fix incorrect condition check for case SNDRV_PCM_TRIGGER_SUSPEND
The regular state before we execute SNDRV_PCM_TRIGGER_SUSPEND should be
SNDRV_PCM_TRIGGER_START, not SNDRV_PCM_TRIGGER_STOP. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 868a6ca84ee7e547ae01a5e04e232e4a392c50b8)
Shengjiu Wang [Tue, 29 Jul 2014 10:39:37 +0000 (18:39 +0800)]
ASoC: cs42xx8: Add SND_SOC_DAIFMT_DSP_A support
According to the spec, the definition of TDM and ONELINE_24 for
CS42XX8_INTF_DAC and CS42XX8_INTF_ADC is wrong. correct them and enable
SND_SOC_DAIFMT_DSP_A support.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 689dc643859953651ffb7111fdbcff2eb0f02841)
The cs42xx8_of_match table is not used outside of the driver, hence it can and
should be made static.
Fixes the following warning from sparse:
sound/soc/codecs/cs42xx8.c:425:27: warning: symbol 'cs42xx8_of_match' was
not declared. Should it be static?
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Brian Austin <brian.austin@cirrus.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit afb7bb45bb904da3704aad47adc4615a81f515c5)
Shengjiu Wang [Fri, 8 Aug 2014 06:47:21 +0000 (14:47 +0800)]
ASoC: fsl_esai: refine esai for TDM support
Original driver didn't store the number of slots, just fix the slot number
to 2, use this default number to calculate bclk and pins for TX/RX.
In this patch, add one parameter for slots, and update the calculation of
bclk and pins of TX/RX. Then driver will be compatible with slots > 2 in
TDM mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit de0d712a6dd1eed097dc6aa4f97ee461949414fe)
ENGR00307592 ASoC: fsl_asrc: Add delay after enabling ASRC p2p
When using ASRC p2p as a for-end with other back-end modules like ESAI,
it'd be safer to add 1ms delay, less might be futile for extreme cases,
after enabling ASRC so as to keep ASRC output FIFO with enough data to
content the DMA burstsize of back-ends and accordingly prevent underrun
that might happen to them.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit c68c1874c07c30a3483eed70fb2abe82e19d1d20)
ENGR01330740-3 ARM: IMX6SL-EVK: correct some clock settings for epdc and lcdif
1. split 'csi_lcdif_sels' into 'csi_core_sels' and 'lcdif_axi_sels'.
2. add 'CLK_SET_RATE_PARENT' flag to clocks 'IMX6SL_CLK_LCDIF_PIX_SEL'
and 'IMX6SL_CLK_EPDC_PIX_SEL'.
3. configure LCDIF's clocks 'IMX6SL_CLK_LCDIF_AXI_SEL' and
'IMX6SL_CLK_LCDIF_AXI'.
4. disable eink's auto update mode.
Shengjiu Wang [Wed, 17 Sep 2014 08:42:51 +0000 (16:42 +0800)]
ENGR00331799-6: ASoC: fsl_spdif: add spba clk support
spdif need to enable the spba clock, when sdma is using share peripheral
script. If don't enable it, may cause the read/write wrong data from/to
registers.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Wed, 17 Sep 2014 08:42:32 +0000 (16:42 +0800)]
ENGR00331799-5: ASoC: fsl_esai: add spba clock support
esai need to enable the spba clock, when sdma is using share peripheral
script. If don't enable it, may cause the read/write wrong data from/to
register.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Wed, 17 Sep 2014 08:42:09 +0000 (16:42 +0800)]
ENGR00331799-4: ASoC: fsl_asrc: add spba clock support
asrc need to enable the spba clock, when sdma is using share peripheral
script. If don't enable it, may cause the read/write wrong data from/to
register.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Tue, 16 Sep 2014 11:18:49 +0000 (19:18 +0800)]
ENGR00331799-2 ASoC: fsl_spdif: don't change the root clock rate of spdif in driver
The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change the clock rate in driver.
In this patch remove the clk_set_rate and clk_round_rate to protect the
clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Thu, 4 Sep 2014 09:28:04 +0000 (17:28 +0800)]
ENGR00331799-1 ASoC: fsl_ssi: refine ipg clock usage in this module
Check if ipg clock is in clock-names property, then we can move the
ipg clock enable and disable operation to startup and shutdown, that
is only enable ipg clock when ssi is working and keep clock is disabled
when ssi is in idle.
But when the checking is failed, remain the clock control as before.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
net: fec: Workaround for imx6sx enet tx hang when enable three queues
When enable three queues on imx6sx enet, and then do tx performance
test with iperf tool, after some time running, tx hang.
Found that:
If uDMA is running, software set TDAR may cause tx hang.
If uDMA is in idle, software set TDAR don't cause tx hang.
There is a TDAR race condition for mutliQ when the software sets TDAR
and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
This will cause the udma_tx and udma_tx_arbiter state machines to hang.
The issue exist at i.MX6SX enet IP.
So, the Workaround is checking TDAR status four time, if TDAR cleared by
hardware and then write TDAR, otherwise don't set TDAR.
The patch is only one Workaround for the issue ERR007885.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
net: fec: add interrupt coalescence feature support
i.MX6 SX support interrupt coalescence feature
By default, init the interrupt coalescing frame count threshold and
timer threshold.
Supply the ethtool interfaces as below for user tuning to improve
enet performance:
rx_max_coalesced_frames
rx_coalesce_usecs
tx_max_coalesced_frames
tx_coalesce_usecs
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
crypto: testmgr - avoid DMA mapping from text, rodata, stack
With DMA_API_DEBUG set, following warnings are emitted
(tested on CAAM accelerator):
DMA-API: device driver maps memory from kernel text or rodata
DMA-API: device driver maps memory from stack
and the culprits are:
-key in __test_aead and __test_hash
-result in __test_hash
MAX_KEYLEN is changed to accommodate maximum key length from
existing test vectors in crypto/testmgr.h (131 bytes) and rounded.
Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
(cherry picked from commit 29b77e5dd88e1b920e3e65681f0e7b961ebbdeb8)
Tadeusz Struk [Mon, 19 May 2014 16:51:33 +0000 (09:51 -0700)]
crypto: testmgr - Fix DMA-API warning
With DMA-API debug enabled testmgr triggers a "DMA-API: device driver maps memory from stack" warning, when tested on a crypto HW accelerator.
Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
(cherry picked from commit 9bac019dad8098a77cce555d929f678e22111783)
Some boards use another WDOG reset source to reboot system in ldo-bypass mode.
We need add the property in board dts file so that we can easily know the
WDOG reset source currently.
For Sabresd, WDOG1 for ldo-enable mode(WDOG event), WDOG2 for ldo-bypass mode
(reset external pmic to trigger POR event).
For sl-evk board, there is no WDOG pin connected with external pmic as Sabresd
, because mx6sl boot at 400Mhz. Then both ldo-enable and ldo-bypass mode use
the common WDOG1 as reset source.
Robin Gong [Thu, 14 Nov 2013 05:58:21 +0000 (13:58 +0800)]
ENGR00287983-2 imx restart: add another WDOG2 reset support for ldo-bypass
For ldo-bypass mode on i.MX6Q/DL sabresd board, we will use another WDOG2 to
reset external pmic to trigger POR event, rather than WDOG1 to trigger WDOG
event in ldo-enable mode. We need to consider it in common mxc_restart().
On i.MX6SL sabresd board we use WDOG1 to trigger WDOG event both ldo-bypass and
ldo-enable mode.
Remove useless code for release interrupt enabled, because we check status by
timer rather than release interrupt. Remove the code which may disable depress
interrupt. Also make sure enable depress interrupt in suspend function.
Robin Gong [Tue, 10 Jun 2014 03:56:49 +0000 (11:56 +0800)]
ENGR00318936-1 input: keyboard: imx: add pm_stay_awake and pm_relax
There is a small window after system suspend but timer scan function
didn't finish timely, in this case, system enter suspend without kpp
interrupt enabled and failed to resume back if key depressed.We add
pm_stay_awake and pm_relax to make sure system suspend flow abort in
this case.
Shengjiu Wang [Tue, 16 Sep 2014 06:08:11 +0000 (14:08 +0800)]
ENGR00331085-5: ARM: dts: imx6sl-evk: Add WM8962 support for imx6sl-evk
Add WM8962 support for imx6sl-evk:
* Add pinctrl group for audmux on evk board
* Add WM8962-related devictree binding for evk board
* Add clock route for ssi.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Enable sound-cs42888 in sabreauto board. Enable clock route for esai
from external 24.576MHz OSC to internal ESAI clock via analog clock2
PADs on the SoC and pll4 so that ESAI can get an entirely synchronous
clock source against CS42888.
Enable i.MX6SX adc driver. ADC driver will try getting ADC controller
channel number via device tree, because i.MX chip enable 4 channels
on each controller.