Paulo Zanoni [Wed, 17 Apr 2013 21:15:49 +0000 (18:15 -0300)]
drm/i915: implement WADPOClockGatingDisable for LPT
This should prevent mode set failures on LPT.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Pimp the w/a tag to fit into Damien's new scheme.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Fri, 10 May 2013 13:01:51 +0000 (14:01 +0100)]
drm/i915: Compute WR PLL dividers dynamically
Up to now, we were using a static table to match the clock frequency
with a (r2,n2,p) triplet. Despite this table being big, it's by no mean
comprehensive and we had to fall back to the closest frequency when the
requested TMDS clock wasn't in the table.
This patch computes (r2,n2,p) dynamically and get rid of The Big Table.
v2: Replace the floating point constant 1e6 by 1000000
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58497 Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
[danvet: s/ /^T/] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Thu, 9 May 2013 17:20:50 +0000 (14:20 -0300)]
drm/i915: HSW FBC WaFbcDisableDpfcClockGating
Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: Ville suggested to enable it back when disabling fbc to avoid wasting
power.
v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Mon, 6 May 2013 22:37:33 +0000 (19:37 -0300)]
drm/i915: Add support for FBC on Ivybridge.
This patch introduce Frame Buffer Compression (FBC) support for IVB,
without enabling it by default.
It adds a new function gen7_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_IVYBRIDGE checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
* Fix DPFC initial write to avoid let trash on the register.
v3: Checking for bad plane on intel_update_fbc() as Chris suggested.
v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0.
v5: Up to v4 this work was entirely focused on Haswell. However Ville
noticed I could reuse the FBC work done for HSW and get FBC for free
at Ivybridge. So it makes more sense enable FBC for IVB first.
FBC for HSW comming on next patches. We are just not enabling it by
default on IVB.
v6: Fix confused commit name (by Matt Turner).
v7: Remove gtt_offset shift since it is page aligned byte offset (by Ville).
Cc: Matt Turner <mattst88@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Thu, 9 May 2013 23:03:18 +0000 (20:03 -0300)]
drm/i915: Organize VBT stuff inside drm_i915_private
drm_i915_private is getting bigger and bigger when adding new vbt stuff.
So, the better way of getting drm_i915_private organized is to create
a special structure for vbt stuff.
v2: Basically conflicts fixes
Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Apr 2013 12:01:43 +0000 (14:01 +0200)]
drm/i915: rip out TV-out lore ...
This seems to be an impressive piece of copy&pasta lore. I've
checked all docs and on most platforms these bits are all MBZ, with
the exception of the SDVO pixel multiplier on gen3. On gen4 that
moved to a special DPLL_MD registers.
No indication whatsoever that we actually need this for native
TV-out support. I suspect this started as a hack when we didn't
yet have proper pixel multiplier support in place for SDVO TV, but
then got stuck in a life of its own.
Just rip it out.
Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Apr 2013 12:01:42 +0000 (14:01 +0200)]
drm/i915: drop TVclock special casing on ilk+
TV-out uses the same reference clock as everyone else. The only
difference seems to be in the slightly different CB tuning limit.
Note that PLL_REF_INPUT_TVCLKINBC is a reserved value on ilk+. Also
strictly speaking we don't support native TV-out on ilk+, hence all
that code is dead. But Bspec still contains some residual mentions of
native TV-out on some pch-split platforms, so I've figured it doesn't
hurt to keep the code around a bit longer (e.g. in the cb tune
function).
v2: Improve the commit message as Jani suggested in his review.
Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Apr 2013 12:01:41 +0000 (14:01 +0200)]
drm/i915: move sdvo TV clock computation to intel_sdvo.c
We have a very nice infrastructure for this now!
Note that the multifunction sdvo support is pretty neatly broken: We
completely ignore userspace's request for which connector to wire up
with the encoder and just use whatever the last detect callback has
seen.
Not something I'll fix in this patch, but unfortunately something
which is also broken in the DDI code ...
v2: Don't call sdvo_tv_clock twice.
Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Wed, 8 May 2013 17:45:14 +0000 (10:45 -0700)]
drm/i915: allow stolen, pre-allocated objects to avoid GTT allocation v2
In some cases, we may not need GTT address space allocated to a stolen
object, so allow passing -1 to the preallocated function to indicate as
much.
v2: remove BUG_ON(gtt_offset & 4095) now that -1 is allowed (Ville)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Wed, 8 May 2013 17:45:13 +0000 (10:45 -0700)]
drm/i915: BIOS and power context stolen mem handling for VLV v7
But we need to get the right stolen base and make pre-allocated objects
for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a
power context, we allocate one here too, from stolen space as required
by the docs.
v2: fix stolen to phys if ladder (Ben)
keep BIOS reserved space out of allocator altogether (Ben)
v3: fix mask of stolen base (Ben)
v4: clean up preallocated object on unload (Ben)
don't zero reg on unload (Jesse)
fix mask harder (Jesse)
v5: use unref for freeing stolen bits (Chris)
move alloc/free to intel_pm.c (Chris)
v6: NULL pctx at disable time so error paths work (Ben)
v7: use correct PCI device for config read (Jesse)
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 18:09:10 +0000 (21:09 +0300)]
drm/i915: Re-enable FBC WM if the watermark is good on gen6+
If the calculated FBC watermark is no good, we simply disable FBC
watermarks. But we fail to re-enable them later if the calculated
watermark becomes good again. Fix that, but remember to leave FBC
watermarks disabled on ILK since that's required by some workarounds.
v2: Fix checkpatch complaint
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imre Deak [Wed, 17 Apr 2013 11:04:50 +0000 (14:04 +0300)]
drm/i915: HSW: allow PCH clock gating for suspend
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: Add bit field to record which pins have received HPD events (v3)
added a bit field for hotplug event tracking. There ended up being three
different v3 of the patch: [1], [2], and [3]. Apparently [1] was the
correct one, but some frankenstein combination of the three got
committed, which reversed the logic for setting the hotplug bits and
misplaced a continue statement, skipping the hotplug irq storm handling
altogether.
This lead to broken hotplug detection, bisected to
commit 321a1b3026ea194dd084cf3bda1e235b2986b0af
Author: Egbert Eich <eich@suse.de>
Date: Thu Apr 11 16:00:26 2013 +0200
drm/i915: Only reprobe display on encoder which has received an HPD event (v2)
which uses the incorrectly set hotplug event bits.
Paulo Zanoni [Fri, 3 May 2013 15:15:38 +0000 (12:15 -0300)]
drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state
In the error state function we read the registers without checking if
the power well is on, so after doing this we have to clear the
FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting
it and printing an error message.
The first version of this patch was checking for the power well state
and then avoiding reading registers that were off, but the reviewers
requested to just read the registers any way and then later clear the
FPGA_DBG_RM_NOCLAIM bit.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Fri, 3 May 2013 15:15:36 +0000 (12:15 -0300)]
drm/i915: add intel_display_power_enabled
This should replace intel_using_power_well. The idea is that we're
adding the requested power domain as an argument, so this might enable
the code to look less platform-specific and also allows us to easily
add new domains in case we need.
v2: Add more domains to enum intel_display_power_domain
v3: Even more domains requested
Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Thu, 2 May 2013 17:48:09 +0000 (10:48 -0700)]
drm/i915: set proper DPIO post divider for VGA on VLV v4
Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
that doesn't actually work as well as the high freq divider here in
practice, just use the high freq divider all the time.
v2: remove unconditional write (Jesse)
check for pixel rate properly (Jesse)
v3: give up, the DAC divider apparently doesn't work, and low res modes
work ok (Jesse)
remove debug msg (Jesse)
In refactoring this, it was only applied to eDP, which is incorrect. In
fact, if we ever use the panel fitter to deal with overscan on HDMI,
we'll need to extend it again, so just drop the conditional altogether.
v2: drop check for eDP since we can use the fitter in any config (Daniel)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: Fix declaration of intel_gmbus_{is_forced_bit/is_port_falid}
Description:
intel_gmbus_is_forced_bit is no extern as its body is right below.
Likewise for intel_gmbus_is_port_valid.
This fixes a compilation issue with clang. An initial version of this patch
was developed by PaX Team <pageexec at freemail.hu>.
This is respin of this patch.
Ben Widawsky [Wed, 24 Apr 2013 06:15:30 +0000 (23:15 -0700)]
drm/i915: BUG_ON bad PPGTT offset
Because PPGTT PDEs within the GTT are calculated in cachelines
(HW guys consistency ftw) we do a divide which will wreak havoc if this
is wrong, and I know that from experience).
If/when we move to multiple PPGTTs this will have to become a WARN, and
return an error. For now however it should always be considered fatal,
and only a developer could hit it.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: s/BUG/WARN] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Wed, 24 Apr 2013 06:15:29 +0000 (23:15 -0700)]
drm/i915: Assert mutex_is_locked on context lookup
Because our context refcounting doesn't grab a ref at lookup time, it is
unsafe to do so without the lock.
NOTE: We don't have an easy way to put the assertion in the lookup
function which is where this really belongs. Context switching is good
enough because it actually asserts even more correctness by protecting
the default_context.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: s/BUG/WARN/] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 3 May 2013 09:49:49 +0000 (11:49 +0200)]
drm/i915: Apply OCD to data/link m/n register #defines
- PCH_ prefix for pch registers on ibx/cpt/ppt.
- Drop the DP_ from the link defines, redundant.
- Drop the GMCH from the data defines and instead give the special g4x
registers a consistent _G4X postfix.
v2:
- Realign #defines and use tabs (Paulo).
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 3 May 2013 09:49:47 +0000 (11:49 +0200)]
drm/i915: PCH_ prefix for transcoder timings
While at it, also extract a common helper to copy the timings from the
cpu transcoder to the pch transcoder. That way it's really explicit
how the lpt transcoder is hardcoded.
v2:
- Re-align #defines properly (Paulo).
- Use cpu_transcoder when copying pipe timings (Paulo).
- s/intel_pch_transcoder_enable/intel_pch_transcoder_set_timings/
since we already have a pch transcoder enable function, and this is
clearer, too.
- Fixup 80 char line overflow in intel_display.c. I've opted to ignore
this in i915_reg.h and i915_ums.c since meh.
Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 3 May 2013 09:49:51 +0000 (11:49 +0200)]
drm/i915: fix up adjusted_mode tracking for interlaced modes
With the hw state readout&check code it's important that the values we
keep around are the canonical ones. Unfortunately when adding the pipe
timings readout support I've missed that the write side adjusts the
timings in the pipe config.
Fix this up and so prevent the unsightly WARN noise in dmesg. This
regression has been introduced in
drm/i915: hw state readout support for pipe timings
Reported-by: Paulo Zanoni <przanoni@gmail.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Thu, 2 May 2013 13:48:08 +0000 (16:48 +0300)]
drm/i915: add context into request struct
Storing context reference into request struct
allows us to inspect context and its associated
objects when requests are retired.
Both ppgtt and arb robustness work will need
this.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Thu, 2 May 2013 13:48:07 +0000 (16:48 +0300)]
drm/i915: put context upon switching
In order to be notified of when the context and all of its associated
objects is idle (for if the context maps to a ppgtt) we need a callback
from the retire handler. We can arrange this by using the kref_get/put
of the context for request tracking and by inserting a request to
demarque the switch away from the old context.
[Ben: fixed minor error to patch compile, AND s/last_context/from/] Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Thu, 2 May 2013 22:30:47 +0000 (15:30 -0700)]
drm/i915: fix Haswell pfit power well check v2
We can't read the pfit regs if the power well is off, so use the cached
value.
v2: re-add lost comment (Jesse)
make sure the crtc using the fitter is actually enabled (Jesse)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop now unused dev_priv, as spotted by Mika.] Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Fri, 3 May 2013 13:29:08 +0000 (16:29 +0300)]
drm/i915: unreference default context on module unload
Before module unload is called, gpu_idle() will switch
to default context. This will increment ref count of base
object as the default context is 'running' on module unload
time. Unreference the drm object so that when context
is freed, base object is freed as well.
v2: added comment to explain the refcounts (Ben Widawsky)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Apr 2013 12:01:40 +0000 (14:01 +0200)]
drm/i915: simplify DP/DDI port width macros
If we ever leak a non-DP compliant port width through here, we have a
pretty serious issue. So just rip out all these WARNs - if we need
them it's probably better to have them at a central place where we
compute the dp lane count.
Also use the new DDI width macro for FDI mode.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: fixup the embarrassing s/intel_dp->DP/temp/ mistake Paulo
spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Tue, 30 Apr 2013 10:30:33 +0000 (13:30 +0300)]
drm/i915: reference count for i915_hw_contexts
Enabling PPGTT and also the need to track which context was guilty of
gpu hang (arb robustness enabling) have put pressure for struct i915_hw_context
to be more than just a placeholder for hw context state.
In order to track object lifetime properly in a multi peer usage, add reference
counting for i915_hw_context.
v2: track i915_hw_context pointers instead of using ctx_ids
(from Chris Wilson)
v3 (Ben): Get rid of do_release() and handle refcounting more compactly.
(recommended by Chis)
v4: kref_* put inside static inlines (Daniel Vetter)
remove code duplication on freeing context (Chris Wilson)
v5: idr_remove and ctx->file_priv = NULL in destroy ioctl (Chris)
This actually will cause a problem if one destroys a context and later
refers to the idea of the context (multiple contexts may have the same
id, but only 1 will exist in the idr).
v6: Strip out the request related stuff. Reworded commit message.
Got rid of do_destroy and introduced i915_gem_context_release_handle,
suggested by Chris Wilson.
v7: idr_remove can't be called inside idr_for_each (Chris Wilson)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v5) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> (v7) Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Squash sob lines, the patch ping-ponged between Ben and Mika
a bit ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 15:52:39 +0000 (18:52 +0300)]
drm/i915: Relax the sprite scaling limits checks
Reduce the size of the the src/dst viewport to keep the scalign ratios
in check.
v2: Below min size sprite handling squashed to previous patch
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 15:52:38 +0000 (18:52 +0300)]
drm/i915: Implement proper clipping for video sprites
Properly clip the source when the destination gets clipped
by the pipe dimensions.
Sadly the video sprite hardware is rather limited so it can't do proper
sub-pixel postitioning. Resort to truncating the source coordinates to
(macro)pixel boundary.
The scaling checks are done using the strict drm_region functions.
Which means that an error is returned when the min/max scaling
ratios are exceeded.
Also do some additional checking against various hardware limits.
v2: Truncate src coords instead of rounding to avoid increasing src
viewport size, and adapt to changes in drm_calc_{h,v}scale().
v3: Adapt to drm_region->drm_rect rename. Fix misaligned crtc_w for
packed YUV formats when scaling isn't supported.
v4: Use stricter scaling checks, use drm_rect_equals()
v5: If sprite is below min size, make it invisible instead returning
an error.
Use WARN_ON() instead if BUG_ON(), and add one to sanity check the
src viewport size.
v6: Add comments to remind about src and dst coordinate types
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 15:52:37 +0000 (18:52 +0300)]
drm: Add drm_rect_equals()
drm_rect_equals() tells whether two drm_rects are equal.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 15:52:36 +0000 (18:52 +0300)]
drm: Add drm_rect_debug_print()
Add a debug function to print the rectangle in a human readable format.
v2: Renamed drm_region to drm_rect, the function from drm_region_debug
to drm_rect_debug_print(), and use %+d instead of +%d in the format.
v3: Use %d format for width/height in the non fixed point case as well
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
These functions calculate the scaling factor based on the source and
destination rectangles.
There are two version of the functions, the strict ones that will
return an error if the min/max scaling factor is exceeded, and the
relaxed versions that will adjust the src/dst rectangles in order to
keep the scaling factor withing the limits.
v2: Return error instead of adjusting regions, refactor common parts
into one function, and split into strict and relaxed versions.
v3: Renamed drm_region to drm_rect, add "_rect_" to the function
names.
v4: Fix "calculcate" typos
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 24 Apr 2013 15:52:34 +0000 (18:52 +0300)]
drm: Add struct drm_rect and assorted utility functions
struct drm_rect represents a simple rectangle. The utility
functions are there to help driver writers.
v2: Moved the region stuff into its own file, made the smaller funcs
static inline, used 64bit maths in the scaled clipping function to
avoid overflows (instead it will saturate to INT_MIN or INT_MAX).
v3: Renamed drm_region to drm_rect, drm_region_clip to
drm_rect_intersect, and drm_region_subsample to drm_rect_downscale.
v4: Renamed some function parameters, improve kernel-doc comments a bit,
and actually generate documentation for drm_rect.[ch].
v5: s/RETUTRNS/RETURNS/
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 25 Apr 2013 20:52:18 +0000 (22:52 +0200)]
drm/i915: move border color writes to pfit_enable
Writing hw registers from compute_config?
Just say no!
In this case not too horrible since we write a constant 0, and only
debugging would put something else in there. But while checking that
code I've noticed that this register disappeared on pch platforms, so
fix that up, too.
And adjust the comment a bit, it's outdated.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 25 Apr 2013 20:52:17 +0000 (22:52 +0200)]
drm/i915: rip out indirection for pfit pipe_config assignment
This was still required a bit (on the cargo-cult side though) when the
state was stored in dev_priv, and when the enable/disable sequence was
botched a bit (to avoid too many updates).
But with pipeconfig we always get a clean slate, so this is pointless.
Rip it out.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 25 Apr 2013 20:52:16 +0000 (22:52 +0200)]
drm/i915: move lvds_border_bits to pipe_config
pipe_config is the new dev_priv!
More seriously, this is actually better since a pipe_config can be
thrown away if the modeset compute config stage fails. Whereas any
state stored in dev_prive needs to be painstakingly restored, since
otherwise a dpms off/on will wreak massive havoc. Yes, that even
applies to state only used in ->mode_set callbacks, since we need to
call those even for dpms on when the Haswell power well cleared
everything out.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Mon, 29 Apr 2013 10:02:54 +0000 (13:02 +0300)]
drm/i915: cleanup opregion asle pipestat enable
Both intel_opregion_enable_asle() and intel_enable_asle() have shrunk
considerably. Merge them together into a static function in i915_irq.c,
and rename to better reflect the purpose and the related platforms.
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Mon, 29 Apr 2013 10:02:53 +0000 (13:02 +0300)]
drm/i915: cleanup redundant checks from intel_enable_asle
Realize that intel_enable_asle() is never called on PCH-split platforms
or on VLV. Rip out the GSE irq enable for PCH-split platforms, which
also happens to be incorrect for IVB+.
This should not cause any functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Mon, 29 Apr 2013 10:02:52 +0000 (13:02 +0300)]
drm/i915: untie opregion init and asle irq/pipestat enable
Stop calling intel_opregion_enable_asle() and consequently
intel_enable_asle() on opregion init. It should not be necessary for
these reasons:
1) On PCH split platforms, it only enables GSE interrupt, which is
enabled in irq postinstall anyway. Moreover, the irq enable uses the
wrong bit on IVB+.
2) On gen 2, it would enable a reserved pipestat bit. If there were gen
2 systems with opregion asle support, that is. And the gen 2 irq
handler won't handle it anyway.
3) On gen 3-4, the irq postinstall will call
intel_opregion_enable_asle() to enable the pipestat.
In short, move the asle irq/pipestat enable responsibility to irq
postinstall, which already happens to be in place.
This should not cause any functional changes, but only do the one line
change here for easier bisectability, just in case, and leave all the
cleanups this allows to followup patches.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Only set ASLE driver readiness (ARDY) and technology enabled indicator
(TCHE) once per opregion init. There should be no need to do that at irq
postinstall time. Also clear driver readiness at fini.
While at it, add defines for driver readiness.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 29 Apr 2013 19:56:12 +0000 (21:56 +0200)]
drm/i915: hw state readout support for pipe timings
This does duplicate the logic in intel_crtc_mode_get a bit, but the
issue is that we also should handle interlace modes and other insanity
correctly.
Hence I've opted for a sligthly more elaborate route where we first
read out the crtc timings for the adjusted mode, and then optionally
(not sure if we really need it) compute the modeline from that.
v2: Also read out the pipe source dimensions into the requested mode.
v3: Rebase on top of the moved cpu_transcoder.
v4: Simplify CHECK_FLAGS logic as suggested by Chris Wilson. Also
properly #undef that macro again.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v3)
[danvet: Use the existing mask for interlaced bits, spotted by Mika.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 4 Apr 2013 11:28:53 +0000 (13:28 +0200)]
drm/i915: hw state readout support for fdi m/n
We want to use the fdi m/n values to easily compute the adjusted mode
dotclock on pch ports. Hence make sure the values stored in the pipe
config are always reliable.
v2: Fixup FDI TU readout.
v3: Rebase on top of moved cpu_transcoder.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 20 Feb 2013 23:00:16 +0000 (00:00 +0100)]
drm/i915: implement fdi auto-dithering
So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
into this, among them the default 1080p mode.
The solution is to dither down the pipe a bit so that everything fits,
which this patch implements.
But ports compute their state under the assumption that the bpp they
pick will be the one selected, e.g. the display port bw computations
won't work otherwise. Now we could adjust our code to again up-dither
to the computed DP link parameters, but that's pointless.
So instead when the pipe needs to adjust parameters we need to retry
the pipe_config computation at the encoder stage. Furthermore we need
to inform encoders that they should not increase bandwidth
requirements if possible. This is required for the hdmi code, which
prefers the pipe to up-dither to either of the two possible hdmi bpc
values.
LVDS has a similar requirement, although that's probably only
theoretical in nature: It's unlikely that we'll ever see an 8bpc
high-res lvds panel (which is required to hit the 2 fdi lane limit).
eDP is the only thing which could increase the pipe_bpp setting again,
even when in the retry-loop. This could hit the WARN. Two reasons for
not bothering:
- On many eDP panels we'll get a black screen if the bpp settings
don't match vbt. So failing the modeset is the right thing to do.
But since that also means it's the only way to light up the panel,
it should work. So we shouldn't be able to hit this WARN.
- There are still opens around the eDP panel handling, and maybe we
need additional tricks. Before that happens it's imo no use trying
to be too clever.
Worst case we just need to kill that WARN or maybe fail the compute
config stage if the eDP connector can't get the bpp setting it wants.
And since this can only happen with an fdi link in between and so for
pch eDP panels it's rather unlikely to blow up, if ever.
v2: Rebased on top of a bikeshed from Paulo.
v3: Improve commit message around eDP handling with the stuff
things with Imre.
Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 19 Apr 2013 09:24:33 +0000 (11:24 +0200)]
drm/i915: fixup 12bpc hdmi dotclock handling
We need to multiply the hdmi port dotclock by 1.5x since it's not
really a dotclock, but the 10/8 encoding bitclock divided by 10.
Also add correct limit checks for the dotclock and reject modes which
don't fit. HDMI 1.4 would allow more, but our hw doesn't support that
unfortunately :(
Somehow I suspect 12bpc hdmi output never really worked - we really
need an i-g-t testcase to check all the different pixel modes and
outputs.
v2: Fixup the adjusted port clock handling - we need to make sure that
the fdi link code still gets the real pixelclock.
v3: g4x/vlv don't support 12bpc hdmi output so drop the bogus comment.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Switch dotclock limit check to <= as suggested by Ville.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 29 Apr 2013 17:34:16 +0000 (19:34 +0200)]
drm/i915: move fdi lane configuration checks ahead
This nicely allows us to drop some hacks which have only been used
to work around modeset failures due to lack of fdi lanes.
v2: Implement proper checking for Haswell platforms - the fdi link to
the LPT PCH has only 2 lanes. Note that we already filter out
impossible modes in intel_crt_mode_valid. Unfortunately LPT does not
support 6bpc on the fdi rx, so we can't pull clever tricks to squeeze
in a few more modes.
v2: Rebased on top of Ben Widawsky's num_pipes reorg.
v3: Rebase on top of Ville's pipe debug output ocd rampage.
v4: Fixup rebase fail spotted by Ville.
v5: Fixup rebase fail spotted by Imre Deak. I suck.
Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 14 Feb 2013 15:54:22 +0000 (16:54 +0100)]
drm/i915: split up fdi_set_m_n into computation and hw setup
And also move the computed m_n values into the pipe_config. This is a
prep step to move the fdi state computation completely into the
prepare phase of the modeset sequence. Which will allow us to handle
fdi link bw constraints in a better way.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 29 Apr 2013 17:33:42 +0000 (19:33 +0200)]
drm/i915: hw state readout support for pipe_config->fdi_lanes
v2: Introduce some nice #defines for the FDI lane width fields and put
them to good use. Suggested by Ville.
v3: Fixup the mask vs. shift copy&pasta fail Imre Deak spotted, and
use the shift #define also in the mask.
Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 13 Feb 2013 17:04:45 +0000 (18:04 +0100)]
drm/i915: move intel_crtc->fdi_lanes to pipe_config
We need this for two reasons:
- Correct handling of shared fdi lanes on ivb with fastboot.
- Handling fdi link bw limits when we only have two fdi lanes by
dithering down a bit.
Just search&replace in this patch, no functional change at all.
Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 19 Apr 2013 09:24:38 +0000 (11:24 +0200)]
drm/i915: allow high-bpc modes on DP
Totally untested due to lack of screens supporting more than 8bpc. But
now we should have closed all holes in our bpp handling, so this
should be safe. The last missing piece was 10bpc support for g4x/vlv,
since we directly use the pipe bpp to feed the display link (and
anyway, only the cpt has any means to have a pipe bpp != the display
link bpp).
Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 24 Apr 2013 12:57:17 +0000 (14:57 +0200)]
drm/i915: implement high-bpc + pipeconf-dither support for g4x/vlv
The current code is rather ... ugly. The only thing it managed to pull
off is getting 6bpc on DP working on g4x. Then someone added another
custom hack for 6bpc eDP on vlv. Fix up this entire mess by properly
implementing the PIPECONF-based dither/bpc controls on g4x/vlv.
Note that compared to pch based platforms g4x/vlv don't support 12bpc
modes. g4x is already caught, extend the check for vlv.
The other fixup is to restrict the lvds-specific dithering to early
gen4 devices - g4x should use the pipeconf dither controls. Note that
on gen2/3 the dither control is in the panel fitter even.
v2: Don't enable dithering when the pipe is in 10 bpc mode. Quoting
from Bspec "PIPEACONF - Pipe A Configuration Register, bit 4":
"Programming note: Dithering should only be enabled for 8 bpc or 6
bpc."
v3: Actually drop the old ugly dither code.
v4: Explain in a short comment why g4x/vlv shouldn't dither for 30 bpp
pipes (Jesse).
v5: Also clear the dither type correctly as spotted by Ville.
v6: As Ville pointed out we need to indeed set the dithering both in
the pipeconf register (for DP outputs) and in the LVDS port register
(for LVDS ouputs). Otherwise LVDS panel will not get properly
dithered. The old patch got away with this since it forgot to clear
the LVDS dither bit ...
v7: Remove redundant BPC_MASK clearing, spotted by Ville.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 19 Feb 2013 16:45:00 +0000 (17:45 +0100)]
drm/i915: force bpp for eDP panels
We've had our fair share of woes already which showed that we can't
rely on the bpc limits in the EDID for eDP panels without risking
black screens. So now we limit the depth by what the BIOS recommends
in the VBT:
But that's not enough, since at least the panel on my ASUS Zenbook
Prime here is also unhappy if the bpc is too low. Hence just take the
firmware value and dither to get what flimsy panels want.
Like before we ensure that we don't change the bpp if the firmware
doesn't provide a value, see
drm/i915: do not default to 18 bpp for eDP if missing from VBT
v2: Apparently there are some horribly broken eDP panels around which
only work if the DP link is set up as if we want to driver a 24bpp
mode, but still only work if the data is feed at 18bpp. See
Adjust the patch accordingly and update all the relevant comments.
v3: Give up on the cargo-culting v2 attempt and just enfore the edp
bpp value if it's there. Broken panels be damned!
Cc: Jani Nikula <jani.nikula@intel.com> Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Sat, 27 Apr 2013 11:44:16 +0000 (12:44 +0100)]
drm/i915: Only print the info message about incresing stolen size for FBC once
Instead of repeatedly bombarding the user with a request to reboot and
increase the stolen size with every fb refresh, just inform them the
first time only.
v2: Rearrange code so the hint to increase the amount of memory stolen
by the BIOS is only emitted if we fail to find sufficient stolen memory
for FBC.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Fixup formatting code mismatch that gcc spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: factor out GMCH panel fitting code and use for eDP v3
This gets the panel fitter working on eDP on VLV, and should also apply
to eDP panels on G4x chipsets (if we ever detect and mark an all-in-one
panel as eDP anyway).
A few cleanups are still possible on top of this, for example the LVDS
border control could be placed in the LVDS encoder structure and updated
based on the result of the panel fitter calculation.
Multi-pipe fitting isn't handled correctly either if we ever get a config
that wants to try the panel fitter on more than one output at a time.
v2: use pipe_config for storing pfit values (Daniel)
add i9xx_pfit_enable function for use by 9xx and VLV (Daniel)
v3: fixup conflicts and lvds_dither check
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: fix up botched conflict resolution from Jesse:
- border = LVDS_BORDER_ENABLE was lost for CENTER scaling
- comment about gen2/3 panel fitter scaling was lost
- dev_priv->lvds_dither reintroduced.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 19 Apr 2013 09:14:35 +0000 (11:14 +0200)]
drm/i915: don't force matching p1 for g4x/ilk+ reduced pll settings
g4x dplls and ilk+ pch plls have a separate field for the reduced p1
setting, so this restriction does not apply. Only older platforms have
the restriction that the p1 divisors must match.
This unnecessary restriction has been introduced in
drm/i915: Only look for matching clocks for LVDS downcloc
Note that with lvds the p2 divisors _always_ match for LVDS, and we
don't support auto-downclocking anywhere else. On eDP downclocking
works with separate data m/n settings, using the same link clock.
Cc: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 25 Apr 2013 15:54:44 +0000 (17:54 +0200)]
drm/i915: use pipe_config for lvds dithering
Up to now we've relied on the bios to get this right for us. Let's try
out whether our code has improved a bit, since we should dither
always when the output bpp doesn't match the plane bpp.
- gen5+ should be fine, since we only use the bios hint as an upgrade.
- gen4 changes, since here dithering is still controlled in the lvds
register.
- gen2/3 has implicit dithering depeding upon whether you use 2 or 3
lvds pairs (which makes sense, since it only supports 8bpc pipe
outpu configurations).
- hsw doesn't support lvds.
v2: Remove redudant dither setting.
v3: Completly drop reliance on dev_priv->lvds_dither.
v4: Enable dithering on gen2/3 only when we have a 18bpp panel, since
up-dithering to a 24bpp panel is not supported by the hw. Spotted by
Ville.
v5: Also only enable lvds port dithering on gen4 for 18bpp modes. In
practice this only excludes dithering a 10bpc plane down for a 24bpp
lvds panel. Not something we truly care about. Again noticed by Ville.
v6: Actually git add.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 19 Apr 2013 09:14:33 +0000 (11:14 +0200)]
drm/i915: move dp clock computations to encoder->compute_config
With the exception of hsw, which has dedicated DP clocks which run at
the fixed frequency already, and vlv, which doesn't have optmized
pre-defined dp clock parameters (yet).
v2: Ville asked me to elaborate a bit more on the longer-term goals
wrt dpll settings computation:
So ultimately my idea is that in the compute config stage first the crtc
code puts the default platform pll limits into the pipe_config. Then
encoders can either overwrite that limit structure with their own special
stuff (mostly for lvds madness). Or they can pick some or all of the
parameters (e.g. just the p2 switchover on hdmi, or all the clock
parameters for dp/sdvo tv).
Once that's done then the generic crtc code can fill out any missing bits
(using the find_best_pll code) and then try to assign which pll to use (if
it's a platform with shared plls). In the end the modeset could should
simply write the computed stuff into registers and never be able to fail.
Of course there's still a lot of data to be moved into pipe_config to make
this all happen, hence some of the temporary ugliness.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: create pipe_config->dpll for clock state
While at it, extract a few small helpers for common computations.
v2: Use the newly added helpers more thanks to Ville's trick to
typedef the legacy intel_clock_t as the new-world struct dpll.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
projects / linux-beck.git / log