Ezequiel Garcia [Sat, 24 May 2014 14:17:10 +0000 (11:17 -0300)]
ARM: dts: Specify the NAND ECC scheme explicitly on Armada 385 DB board
The factory bootloader on A385-DB boards expect the ECC strength to be
4 bits over 512 bytes. Hence, we need to specify this in the devicetree,
to prevent the kernel from assuming any different ECC scheme.
Ezequiel Garcia [Sat, 24 May 2014 14:17:09 +0000 (11:17 -0300)]
ARM: dts: Specify the NAND ECC scheme explicitly on Armada 375 DB board
The factory bootloader on A375-DB boards expect the ECC strength to be
4 bits over 512 bytes. Hence, we need to specify this in the devicetree,
to prevent the kernel from assuming any different ECC scheme.
Thomas Petazzoni [Thu, 22 May 2014 12:48:02 +0000 (14:48 +0200)]
ARM: mvebu: returns ll_get_cpuid() to ll_get_coherency_cpumask()
In the refactoring of the coherency fabric assembly code, a function
called ll_get_cpuid() was created to factorize common logic between
functions adding CPU to the SMP coherency group, enabling and
disabling the coherency.
However, the name of the function is highly misleading: ll_get_cpuid()
makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1
for CPU1, etc. In fact, this is not at all what this function returns:
it returns a CPU mask for the current CPU, usable for the coherency
fabric configuration and control registers.
Therefore this commit renames this function to
ll_get_coherency_cpumask(), and adds additional comments on top of the
function to explain in more details what it does, and also how the
endianess issue is handled.
Thomas Petazzoni [Thu, 22 May 2014 12:48:01 +0000 (14:48 +0200)]
ARM: mvebu: improve comments in coherency_ll.S
This commit makes no functional change, it only improves a bit the
various code comments in mach-mvebu/coherency_ll.S, by fixing a few
typos and adding a few more details.
Thomas Petazzoni [Thu, 22 May 2014 12:47:59 +0000 (14:47 +0200)]
ARM: mvebu: fix big endian booting after coherency code rework
As part of the introduction of the cpuidle support for Armada XP, the
coherency code was significantly reworked, especially in the
coherency_ll.S file. However, when the ll_get_cpuid function was
created, the big-endian specific code that switches the endianess of
the register was not updated properly.
This patch fixes this code, and therefore makes big endian systems
bootable again.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 2e8a5942f875 ("ARM: mvebu: Split low level functions to manipulate HW coherency") Reported-by: Kevin Hilman <khilman@linaro.org> Cc: Kevin Hilman <khilman@linaro.org> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Tue, 20 May 2014 15:13:03 +0000 (17:13 +0200)]
ARM: mvebu: coherency: fix registration of PCI bus notifier when !PCI
Commit b0063aad5dd8 ("ARM: mvebu: use hardware I/O coherency also for
PCI devices") added a reference to the pci_bus_type variable, but this
variable is only available when CONFIG_PCI is enabled. Therefore,
there is now a build failure in !CONFIG_PCI situations.
This commit fixes that by enclosing the entire initcall into a
IS_ENABLED(CONFIG_PCI) condition.
Thomas Petazzoni [Tue, 20 May 2014 14:43:28 +0000 (16:43 +0200)]
ARM: mvebu: fix definitions of PCIe interfaces on Armada 38x
Due a copy/paste error, the 'reg' values for the third PCIe interface
on Armada 380, and the third and fourth PCIe interfaces on Armada 385
are wrong: they are equal to the one of the second PCIe interface.
This patch fixes this by using the appropriate 'reg' values for those
PCIe interfaces.
Without this fix, the third and fourth PCIe interfaces are unusable on
those platforms.
Thomas Petazzoni [Thu, 15 May 2014 14:59:34 +0000 (16:59 +0200)]
ARM: mvebu: implement L2/PCIe deadlock workaround
The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
CPU core, the PL310 cache and the Marvell PCIe hardware block are
affected a L2/PCIe deadlock caused by a system erratum when hardware
I/O coherency is used.
This deadlock can be avoided by mapping the PCIe memory areas as
strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
removing the outer cache sync done in software. This is implemented in
this patch by:
* Registering a custom arch_ioremap_caller function that allows to
make sure PCI memory regions are mapped MT_UNCACHED.
* Adding at runtime the 'arm,io-coherent' property to the PL310 cache
controller. This cannot be done permanently in the DT, because the
hardware I/O coherency can only be enabled when CONFIG_SMP is
enabled, in the current kernel situation.
Besides our Kirkwood Reference design, there is another group of board
on which the eth interface is not connected to a phy but to a switch for
some board internal communication. For these designs, the memory also is
raised to 256MB.
The configuration of the switch is handled by an EEPROM or by the
bootloader, but on the kirkwood side, the port is always configured as
1000 Mbits, full duplex.
This file allows to factor the common parts between the various Keymile
Kirkwood Designs.
kirkwood-km_common configures the peripherals that are currently
common to all our Kirkwood designs: PCIe, pinctrl, bitbang I2C, NAND
Flash controller.
The kirkwood-km_kirkwood file is then changed to include this common
file.
The 98DX4122 dtsi file lacks the defintion of the PCIe controller which
is present on this SoC.
The SATA phys must also be explicitely disabled since they are not
present on this SoC. If they remain enabled, a hardlock occures when
their clock gates are enabled.
Gregory CLEMENT [Thu, 15 May 2014 10:17:42 +0000 (12:17 +0200)]
ARM: mvebu: add Device Tree description for the EHCI controllers on Armada 375
The Marvell Armada 375 SoCs contains two EHCI controllers. This commit
adds the Device Tree description of these interfaces at the SoC level,
and also enables the USB2 port on the Armada 375 DB platform.
Gregory CLEMENT [Thu, 15 May 2014 10:17:41 +0000 (12:17 +0200)]
ARM: mvebu: add Device Tree description of the xHCI controller on Armada 375
The Marvell Armada 375 SoCs contain a xHCI controller. This commit
adds the Device Tree description of this interfaces at the SoC level,
and also enables the USB3 port on the Armada 375 DB platform.
Gregory CLEMENT [Thu, 15 May 2014 10:17:40 +0000 (12:17 +0200)]
ARM: mvebu: add Device Tree description of the EHCI controller on Armada 38x
The Marvell Armada 38x SoCs contains one EHCI controller. This commit
adds the Device Tree description of this interface at the SoC level,
and also enables the USB2 port on the Armada 385 DB platform.
Gregory CLEMENT [Thu, 15 May 2014 10:17:39 +0000 (12:17 +0200)]
ARM: mvebu: add Device Tree description of xHCI controllers on Armada 38x
The Marvell Armada 38x SoCs contains two xHCI controllers. This commit
adds the Device Tree description of those interfaces at the SoC level,
and also enables the two USB3 ports on the Armada 385 DB platform and
one USB3 port on the Armada 385 RD platform.
Gregory CLEMENT [Thu, 15 May 2014 10:17:37 +0000 (12:17 +0200)]
ARM: configs: enable XHCI mvebu support in mvebu_v7_defconfig
The Marvell Armada 38x platform needs the xhci_mvebu driver enabled
for the xHCI USB hosts, so this commit enables the corresponding
Kconfig option in mvebu_v7_defconfig.
Thomas Petazzoni [Tue, 13 May 2014 16:04:30 +0000 (18:04 +0200)]
ARM: mvebu: use hardware I/O coherency also for PCI devices
Since the beginning of the introduction of hardware I/O coherency
support for Armada 370 and Armada XP, the special DMA operations
should have applied to all DMA capable devices. Unfortunately, while
the original code properly took into account platform devices, it
didn't take into account PCI devices, which can also be DMA masters.
This commit fixes that by registering a bus notifier on pci_bus_type,
to register our custom DMA operations, like is already done for
platform devices. While doing this, we also rename
mvebu_hwcc_platform_notifier() to mvebu_hwcc_notifier() and
mvebu_hwcc_platform_nb to mvebu_hwcc_nb because they are no longer
specific to platform devices.
Andrew Lunn [Sun, 11 May 2014 19:30:39 +0000 (21:30 +0200)]
ARM: Kirkwood: DT versions of OpenRD boards
Create DTS files to describe the Marvell OpenRD boards.
Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1399836639-1918-1-git-send-email-andrew@lunn.ch Tested-by: Francois Lorrain <francois.lorrain@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 12 May 2014 14:11:40 +0000 (16:11 +0200)]
ARM: mvebu: mvebu-soc-id: keep clock enabled if PCIe unit is enabled
Since the mvebu-soc-id code in mach-mvebu/ was introduced, several
users have noticed a regression: the PCIe card connected in the first
PCIe interface is not detected properly.
This is due to the fact that the mvebu-soc-id code enables the PCIe
clock of the first PCIe interface, reads the SoC device ID and
revision number (yes this information is made available as part of
PCIe registers), and then disables the clock. However, by doing this,
we gate the clock and therefore loose the complex PCIe configuration
that was done by the bootloader.
Unfortunately, as of today, the kernel is not capable of doing this
complex configuration by itself, so we really need to keep the PCIe
clock enabled. However, we don't want to keep it enabled
unconditionally: if the PCIe interface is not enabled or PCI support
is not compiled into the kernel, there is no reason to keep the PCIe
clock running.
This issue was discussed with Kevin Hilman, and the suggested solution
was to make the mvebu-soc-id code keep the clock enabled in case it
will be needed for PCIe. This is therefore the solution implemented in
this patch.
Long term, we hope to make the kernel more capable in terms of PCIe
configuration for this platform, which will anyway be needed to
support the compilation of the PCIe host controller driver as a
module. In the mean time however, we don't have much other choice than
to implement the currently proposed solution.
Reported-by: Neil Greatorex <neil@fatboyfat.co.uk> Cc: Neil Greatorex <neil@fatboyfat.co.uk> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Kevin Hilman <khilman@linaro.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399903900-29977-3-git-send-email-thomas.petazzoni@free-electrons.com Fixes: af8d1c63afcb ("ARM: mvebu: Add support to get the ID and the revision of a SoC") Cc: <stable@vger.kernel.org> # 3.14+: 42a18d1cf484: ARM: mvebu: mvebu-soc-id: add missing clk_put() call Cc: <stable@vger.kernel.org> # 3.14+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The mvebu-soc-id code in mach-mvebu/ needs to enable a clock to read
the SoC device ID and revision number. To do so, it does a clk_get(),
then a clk_prepare_enable(), reads the value, and disables the clock
with clk_disable_unprepare(). However, it forgets to clk_put() the
clock. This commit fixes this issue.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399903900-29977-2-git-send-email-thomas.petazzoni@free-electrons.com Cc: <stable@vger.kernel.org> # 3.14+ Fixes: af8d1c63afcb ("ARM: mvebu: Add support to get the ID and the revision of a SoC") Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler
flags are for ARMv6, and we will get:
/tmp/ccwDEzd0.s: Assembler messages:
/tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb '
/tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb '
/tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb '
/tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb '
make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1
ARM: mvebu: conditionalize Armada 375 coherency workaround
The Armada 375 coherency workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.
ARM: mvebu: conditionalize Armada 375 SMP workaround
The Armada 375 SMP workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.
Note that the initialization of the SMP workaround is delayed from
->smp_prepare_cpus() to ->smp_boot_secondary() because when
->smp_prepare_cpus() is called, the early initcalls have not be
called, so the mvebu-soc-id mechanism is not operational. Since the
workaround is anyway not needed before the secondary CPU is started,
we can delay its implementation until the ->smp_boot_secondary() call.
Currently, the mvebu-soc-id logic is initialized through a
core_initcall(). However, we will soon need to know the SoC revision
before booting secondary CPUs, because a workaround affects Armada 375
Z1 steppings, but should not be applied on Armada 375 A0 steppings.
Unfortunately, core_initcall() are called way too late compared to the
SMP initialization. Therefore, the mvebu-soc-id initialization is move
to an early_initcall(), which is called before the SMP initialization.
In commit 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add
thermal quirk for the Armada 375 DB board'), a check on the Armada SoC
revision was added to decide whether a quirk for the thermal device
should be applied or not.
However, the quirk implementation has a bug: it assumes
mvebu_get_soc_id() returns true on success, but it returns
0. Therefore, the condition:
if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV)
is always false (as long as mvebu-soc-id is properly initialized). As
a consequence, the quirk is always applied, even on A0 steppings, for
which the quirk should not be applied.
This was spotted by testing the thermal driver on Armada 375 A0, which
Ezequiel could not do since he does not have access to the A0 revision
of the SoC for the moment.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board') Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
ARM: mvebu: Add thermal quirk for the Armada 375 DB board
The initial release of the Armada 375 DB board has an Armada 375
Z1 stepping silicon. This commit introduces a quirk that allows
to workaround a series of issues with the thermal sensor in this
stepping, but updating the devicetree:
* Updates the compatible string for the thermal, so the driver
can perform a specific initialization of the sensor.
* Moves the offset of the thermal control register. This quirk
allows to specifiy the correct (A0 stepping) offset in the
devicetree.
ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
l2x0_of_init function is always defined
arch/arm/include/asm/hardware/cache-l2x0.h: in case of
CONFIG_CACHE_L2X0 is not selected then a placeholder is defined.
Then there is no need to have ifdef around l2x0_of_init.
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
Add the wfi, cpu idle and cpu deep idle power states support for the
Armada XP SoCs.
All the latencies and the power consumption values used at the
"armada_370_xp_idle_driver" structure are preliminary and will be
modified in the future after running some measurements and analysis.
Thomas Petazzoni [Mon, 28 Apr 2014 18:20:39 +0000 (20:20 +0200)]
ARM: mvebu: refine which files are build in mach-mvebu
Following the integration into mach-mvebu of the Kirkwood ARMv5
support, we need to be more careful about which files get built. For
example, the pmsu.c file now calls wfi(), which only exists on ARMv7
platforms.
Therefore, this commit changes mach-mvebu/Makefile to build the Armada
370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is
enabled.
ARM: mvebu: Add the PMSU related part of the cpu idle functions
The cpu idle support will need to access to Power Management Service
Unit. This commit adds the architecture related functions that will be
used in the idle path of the cpuidle driver.
ARM: mvebu: Allow to power down L2 cache controller in idle mode
This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.
This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.
ARM: mvebu: Low level function to disable HW coherency support
When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.
ARM: mvebu: Split low level functions to manipulate HW coherency
Actually enabling coherency and adding a CPU on a SMP group are two
different operations which can be done separately. This patch splits
this in two functions.
Moreover as they use common pattern, this patch also creates local low
level functions (ll_get_coherency_base and ll_get_cpuid) to be used by
the exposed functions (ll_add_cpu_to_smp_group and
ll_enable_coherency)
ARM: mvebu: Remove the unused argument of set_cpu_coherent()
set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.
ARM: mvebu: remove the address parameter for ll_set_cpu_coherent
In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.
This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:04 +0000 (15:54 +0200)]
ARM: mvebu: add Armada 38x compatible string to pmsu
Since the Armada 38x PMSU registers are slightly different than the
Armada 370/XP PMSU ones, we introduce a new compatible string
"armada-380-pmsu" in the PMSU driver. These differences are not
visible for the current usage of the PMSU, but they might become
visible in the future.
ARM: mvebu: add workaround for SMP support for Armada 375 stepping Z1
Due to internal bootrom issue, CPU[1] initial jump code (four
instructions) should be placed in SRAM memory of the SoC. In order to
achieve this, we have to unmap the BootROM and at some specific
location where the BootROM was place, create a specific MBus window
for the SRAM. This SRAM is initialized with a few instructions of code
that allows to jump into the real secondary CPU boot address.
This workaround will most likely be disabled when newer steppings of
the Armada 375 will be made available, in which case a dynamic test
based on mvebu-soc-id will be added.
ARM: mvebu: add SMP support for Armada 375 and Armada 38x
This commit adds the SMP support for Armada 375 and Armada 38x. It
turns out that the SMP logic for both of these SOCs are fairly
similar, the only differences being:
* A different method to set the secondary CPU boot address
* An Armada 375 specific workaround needed for the early Z1 stepping,
added by the following patch.
Other than that, the patch is fairly straightforward and adds the
usual platsmp and headsmp code, defining the smp_operations structure
that is referenced from the DT_MACHINE structures.
ARM: mvebu: add function to set the resume boot address for Armada 375
In order to boot the secondary CPUs on Armada 375, we need to set the
boot address of these CPUs, through a register part of the System
Controller (this deviates from the Armada XP design, where the boot
address was defined using a register part of the PMSU unit).
Therefore, this commit adds a new helper function in the System
Controller driver to set the secondary CPU boot address.
Moreover, it moves the System Controller initialization as an
early_initcall(), since arch_initcall() is too late for an SMP-related
initialization.
Thomas Petazzoni [Mon, 14 Apr 2014 13:53:59 +0000 (15:53 +0200)]
ARM: mvebu: use CPU_METHOD_OF_DECLARE for SMP on Armada XP
This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.
Thomas Petazzoni [Mon, 14 Apr 2014 13:53:58 +0000 (15:53 +0200)]
ARM: mvebu: move Armada XP specific SMP initialization to platsmp.c
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets
the boot address of a secondary CPUs and deasserts the reset. However,
the Armada 375 needs a slightly different logic, so it makes more
sense to move this code into the Armada XP specific platsmp.c.
In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function
is exported. It will be needed for both the Armada XP and Armada 38x
SMP implementations.
Non-DT irq handlers were working through irq causes from most-significant
to least-significant bit, while DT irqchip driver does it the other way
round. This revealed some more HW issues on Kirkwood peripheral IP, where
spurious sdio irqs can happen although irqs are masked.
Also, the generated binaries show that original non-DT order compared
to DT order save two instructions for each bit count check:
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:02 +0000 (15:54 +0200)]
irqchip: irq-armada-370-xp: Use cpu notifier to initialize secondary CPUs
Some irqchip initialization must be done on secondary CPUs. On mvebu
platforms, this is currently achieved by having the
arch/arm/mach-mvebu/platsmp.c code directly call into a function
exported by the irqchip driver, which isn't really nice.
This commit changes this by using the same solution as the one used in
the GIC driver: the irqchip driver registers a CPU notifier, which is
used to do the secondary CPU IRQ initialization. This way, the irqchip
driver is completely autonomous, and the function no longer needs to
be exposed from the irqchip driver to the SoC code.
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:01 +0000 (15:54 +0200)]
irqchip: irq-armada-370-xp: Do the set_smp_cross_call() in the driver
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the
set_smp_cross_call() to register the IPI-triggering function, it makes
more sense to do exactly what the GIC driver is doing: let the irqchip
driver do it. This way, it avoids having to expose the
armada_mpic_send_doorbell() function between the irqchip driver and
the SoC code.
Brian Norris [Thu, 1 May 2014 06:26:43 +0000 (23:26 -0700)]
ARM: mvebu: defconfig: add MTD_SPI_NOR (new dependency for M25P80)
These defconfigs contain the CONFIG_M25P80 symbol, which is now
dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy
the new dependency.
At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398925607-7482-9-git-send-email-computersforpeace@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
ARM: dts: kirkwood: set Guruplug ethernet PHY compatible
Ethernet PHY compatible shall be "ethernet-phy-ieee802.3-c22" and
"ethernet-phy-idAAAA.BBBB" if PHY OUI id is known. We know it for
the PHY found on Guruplug, so set it accordingly.
ARM: dts: kirkwood: set default pinctrl for I2C1 on 6282
Currently, the only 6282-based Kirkwood boards that use I2C1 are Openblocks
A6/A7. Both use the same default I2C1 pinctrl setting from kirkwood-6282.dtsi.
Move the pinctrl setting to the I2C1 node directly and put a note in front of
the corresponding pinctrl node to overwrite the setting on board level.
There is only one valid pinctrl setting for I2C0 on Kirkwood. Now that we
have the setting in the common SoC pinctrl, move it to the I2C0 controller
node directly and remove it from the individual boards.
While at it, also fix up status = "okay" to "ok" on one board's I2C0 node.
There is only one valid pinctrl setting for NAND on Kirkwood. Now that we
have the setting in the common SoC pinctrl, move it to the NAND controller
node directly and remove it from the individual boards.
While at it, also fix up status = "okay" to "ok" on one board's NAND node.
Most Kirkwood boards use the default SPI0 pinctrl setting anyway. Add a
default pinctrl setting to the toplevel SoC SPI0 node and put a note
in front of the corresponding pinctrl node to overwrite the setting
on board level.
Currently, only T5325 is using a different setting and already
overwrites the corresponding pinctrl node.
ARM: dts: kirkwood: set default pinctrl for UART0/1
Most boards use the default UART0/1 pinctrl setting without RTS/CTS.
Add the pinctrl setting to the toplevel SoC UART nodes and put a note
in front of the corresponding pinctrl node to overwrite the setting
on board level. Currently, both boards using a different UART pinctrl
setting (Openblocks A6, A7) already overwrite the pinctrl node.
While at it, also fix up some status = "ok" to "okay" and again
whitespace issues on mplcec4 uart nodes.
On Kirkwood, there is only one valid pinctrl setting for GBE1. With
a common SoC pinctrl node, we can now set it in the node instead of
in each board file.
ARM: dts: kirkwood: add pinctrl node to common SoC include
All Kirkwood SoCs have their pinctrl registers at the same address.
Instead of replaying the same reg property on each SoC, have the
reg property set in the common SoC file already. This also allows
us to move common pinctrl settings to this node later on.
ARM: dts: kirkwood: remove clock-frequency properties from UART nodes
UART devices found on Kirkwood SoCs derive their baudrate from TCLK.
With proper clocks property in the SoCs serial node, boards do not
need to overwrite it anymore.
Remove the remaining clock-frequency property from all Kirkwood boards.
ARM: dts: kirkwood: add stdout-path property to all boards
ePAPR allows to reference the device used for console output by
stdout-path property. With node labels for Kirkwood UART0, now
reference it on all Kirkwood boards that already have ttyS0 in
their bootargs property.
While at it, fix some whitespace issues on mplcec4's chosen node
(there are more, but we only fix the chosen node now)
Commit 54397d85349f
("ARM: kirkwood: Relocate PCIe device tree nodes")
moved the pcie-controller nodes for the Kirkwood SoCs to the mbus
bus node. For some reason, two boards were not properly converted
and have their pci-controller nodes still in the ocp bus node.
As the corresponding SoC pcie-controller does not exist anymore,
it is likely that pcie is broken on those boards since above commit.
Fix it by moving the pcie related nodes to the correct location.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Fixes: 54397d85349f ("ARM: kirkwood: Relocate PCIe device tree nodes") Cc: <stable@vger.kernel.org> # v3.12+ Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-2-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:13 +0000 (23:26 +0200)]
memory: mvebu-devbus: add a devbus, keep-config property
Currently, the mvebu-devbus Device Tree binding makes defining the
timing parameters mandatory.
However, in practice, when converting Orion5x platforms to the Device
Tree, we may not necessarily have easy access to the hardware
platforms to fetch those values which were not defined in old-style
board files: all these platforms rely on the bootloader setting the
timing parameters correctly.
In order to facilitate the migration to the Device Tree of this
platform, this commit relaxes the mvebu-devbus Device Tree binding by
introducing a 'devbus,keep-config' boolean property, which, if
defined, will ignore all timing parameters passed in the Device Tree,
and simply rely on the timing values already defined by the
bootloader.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:12 +0000 (23:26 +0200)]
memory: mvebu-devbus: add Orion5x support
This commit adds support for the Orion5x family of Marvell processors
into the mvebu-devbus driver. It differs from the already supported
Armada 370/XP by:
* Having a single register (instead of two) for doing all the timing
configuration.
* Having a few less timing configuration parameters.
For this reason, a separate compatible string "marvell,orion-devbus"
is introduced.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:11 +0000 (23:26 +0200)]
memory: mvebu-devbus: split functions
The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the registers.
Therefore, in preparation to the introduction of Orion5x support, we
separate into two functions the code that 1/ retrieves the timing
parameters from the Device Tree and 2/ applies those timings
parameters into the hardware registers.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:10 +0000 (23:26 +0200)]
memory: mvebu-devbus: use _SHIFT suffixes instead of _BIT
As noted by Sebastian Hesselbarth, the definitions in mvebu-devbus.c
are not bit definition, but rather shift values, so a _SHIFT prefix
would make more sense. This commit therefore replaces the *_BIT
definitions by *_SHIFT definitions.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:09 +0000 (23:26 +0200)]
memory: mvebu-devbus: use ARMADA_ prefix in defines
The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the register. Therefore, in
preparation to the introduction of Orion5x support, we rename the
Armada 370/XP specific definitions to have an ARMADA_ prefix.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:42 +0000 (23:26 +0200)]
ARM: orion: remove no longer needed gpio DT code
Following the move to pure DT-based probing of the GPIO controllers on
Orion5x, some code in plat-orion/orion-gpio.c can be removed as it is
no longer used.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:41 +0000 (23:26 +0200)]
ARM: orion: remove no longer needed DT IRQ code
Following the move of the Orion5x Device Tree support to use
irqchip_init() for the interrupt controller probing, the
plat-orion/irq.c code for DT-probing of the interrupt controller is no
longer necessary, so we can get rid of it.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:40 +0000 (23:26 +0200)]
ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree
This commit converts the Maxtor Shared Storage II Orion5x platform to
the Device Tree. The only remaining things not converted are PCI and
the special power off method.
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:39 +0000 (23:26 +0200)]
ARM: orion5x: convert d2net to Device Tree
This commit converts the LaCie d2 Network platform to the Device Tree.
All devices except LEDs are converted, because the LED code needs a
non-LED GPIO to be set to a given value for the LEDs to work, and this
cannot yet be easily represented in DT.
Also, references to the LaCie Big Disk Network platform are lost,
because this platform apparently has exactly the same hardware support
as the LaCie d2 Network, so their Device Tree files would be
identical.
projects / karo-tx-linux.git / log