ENGR00281017 [MX6SL]Low power IDLE mode optimizations
Added a new bus freq mode - ultra_low_bus_freq_mode.
In this mode the ARM is the only bus master that is active and
the system is already in low power idle mode.
And when ARM executes WFI in this mode, we do some aggressive
power savings techinques like:
1. Drop DDR freq to 1MHz
2. Drop AHB freq to 3MHz
3. Float the DDR IO pads
4. If all PLLs are in bypass (which should be the case), do
some analog power saving options like reducing the OSC-bias current,
turning off the regular bandgap, disabling the regular 2P5, enabling
the weak 2p5 etc.
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
ENGR00280852-9 mxc: asrc: Use threshold to clear dma request
Previously, we used sdma's event pending to forcibly re-schedule sdma
for work round, because sdma channel for ASRC input task would fail to
be opened due to its dma request always keeping high after ASRC opens
the pair, which cause sdma miss the trigger point of dma request.
Now, instead of using event pending, we clear the dma request on ASRC
driver side by setting its thresholds to an impossible trigger area
during its stall state. Since ASRC would stall its process when input
fifo is near empty or output fifo is near full, during the stall state,
the specific thresholds, 0 for input fifo and 63 for output fifo, would
never let asrc meet this condition. So dma request can be cleared and
raised again after we restore the true required thresholds.
Accordingly, since we don't need event pending any more, we dropped the
code from the sdma driver.
ENGR00280852-7 mxc: asrc: Only set ASRC to STALL level in start_conv()
We don't need to set ASRC to STALL level everytime, instead we only need
to do that at the beginning. If we insert null data into input fifo during
the sequence of valid datas, there would be a noise occur to it.
By doing this, we can assure ASRC would keep each period's perturbation of
output dma task within 8 sample sizes, which is the default value for last
period number. Thus we don't need to expand the last period number any more.
This patch also dropped some unused functions since the driver no long needs
them and replaced wrapped function for channel number configuration with direct
regmap_update_bits() to make the driver clean.
ENGR00280852-3 mxc: asrc: Use regmap to control register accessing
Dropped the legency readl/writel() and use regmap instead. Also removed
core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to
regmap already has these features.
This patch also added a missing writable register to the regmap in order
to assure the regsiter updating success.
regmap: Make regmap-mmio usable from atomic contexts
regmap-mmio uses a spinlock with spin_lock() and spin_unlock() for locking.
To be able to use the regmap API from different contexts (atomic vs non-atomic),
without the risk of race conditions, we need to use spin_lock_irqsave() and
spin_lock_irqrestore() instead. A new field, the spinlock_flags field, is added
to regmap struct to store the flags between regmap_{,un}lock_spinlock(). The
spinlock_flags field itself is also protected by the spinlock.
Thanks to Stephen Warren for the suggestion of this particular solution.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
ENGR00281611 i2c: imx: update i2c clock divider for each transaction
i.MX6 I2C clk is from IPG_PERCLK which is sourced from IPG_CLK.
Under normal operation, IPG_CLK is 66MHz, ipg_perclk is at 22MHz.
In low bus freq mode, IPG_CLK is at 12MHz and IPG_PERCLK is down
to 4MHz. So the I2C driver must update the divider register for
each transaction when the current IPG_PERCLK is not equal to the
clock of previous transaction.
Robby Cai [Thu, 26 Sep 2013 09:57:18 +0000 (17:57 +0800)]
ENGR00281446 ARM: dts: imx6: correct the power supply node name for epdc
The naming convention for power supply node in DTS is "%s-supply".
With this patch regulator_get() will process in the DT way rather than
traditional way. This patch has no functional impact.
The overlay framebuffer's position and resolution are
set with two different APIs. They depend on each other to
make sure the overlay framebuffer window will not go out
of the background framebuffer window. Potentially, this
causes the overlay framebuffer's position or resolution
of the current video pipeline be impacted by the settings
of the last time. To setup the overlay fb from scratch
correctly, this patch takes the following steps:
- blank framebuffer
- set framebuffer position to the starting point
- reconfigure framebuffer
- set framebuffer position to a specific point
- unblank framebuffer
This procedure applies to non-overlay framebuffers as well.
Liu Ying [Thu, 26 Sep 2013 05:41:17 +0000 (13:41 +0800)]
ENGR00279204-1 mxc vout: reconfig fb when necessary
Users may call VIDIOC_S_CTRL or VIDIOC_S_CROP ioctrls
to update streaming parameters on-the-fly after video
has been streamed on, such as for rotation/output
resolution/overlay output position change. Any
unnecessary frame buffer reconfiguration would cause
a pair of frame buffer blank/unblank events happen and
even makes the background framebuffer show up for a
short period of time if the video is rendered on an
overlay framebuffer. This patch compares the last time
video output pipe line settings with the current ones
to determine whether frame buffer reconfiguration is
necessary or not.
ENGR00279946 dts: imx6qdl-sabreauto: add baseboard sd card slot support
NOTE since SD Card in main board takes a long route hence with
Drive Speed High 80 OHMS causing error on high speed cards.
Per suggestion DSE 40 OHMS is used.
Robby Cai [Sun, 22 Sep 2013 09:31:06 +0000 (17:31 +0800)]
ENGR00280140 pxp/v4l2: restore the display content after video playback finishes
After finish video playback, the last frame remains on the display.
It's because the UI display start address (smem_start) has been changed when
do video playback but not changed back again after the playback finishes.
From the function call point of view,
pxp_set_fbinfo() // pxp->fb.base tracks right addr for UI framebuffer
pxp_show_buf(toshow) // smem_start changed to v4l2 display addr
pxp_set_fbinfo() // pxp->fb.base changed to v4l2 display addr
pxp_show_buf(not toshow) // smem_start still equal to v4l2 display addr
// for pan_display
This patch fixes it by calling pxp_set_fbinfo once in open function.
ENGR00281036: [MX6SL]Align LPDDR2 freq change code to 8-byte boundary
This patch fixes 4 issues:
1. Add the .align 8 directive to the LPDDR2 freq change code,
else the fncpy() function fails and the kernel does not boot.
2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code
3. Fix the warning in clk_imx6sl.c
4. Change dev_WARN to dev_info in busfreq-imx6.c.
ARM: dts: imx6q: fix the wrong offset of the Pad Mux register
The patch "0b7a76a ARM: dts: imx6q{dl}: add DTE pads for uart"
adds the DTE pads for uart. For PAD_EIM_D29, the offset of the
Pad Mux register should be 0x0c8, not 0x0c4.
ENGR00279545 [MX6x:Cpufreq] Initialize mutex before driver registration
The mutex, set_cpufreq_lock, should be initialized before the driver is
registered. Else if the default governor is set to performance or ondemand,
the cpufreq driver will try to set the freq to the max freq supported and
this will cause a crash during boot.
Robby Cai [Thu, 12 Sep 2013 11:11:54 +0000 (19:11 +0800)]
ENGR00279413 pxp/v4l2: get the right framebuffer start address at run time
Previously the driver gets the framebuffer start address at probe time.
But this address might be changed if the framebuffer drivers re-allocate
the frame buffers due to the application changes the yres_virtual.
As a result, some garbage data can be observed on display.
This patch adjusts the way to detect the start address at run time to
fix this problem.
Some boards use another WDOG reset source to reboot system in ldo-bypass mode.
We need add the property in board dts file so that we can easily know the
WDOG reset source currently.
For Sabresd, WDOG1 for ldo-enable mode(WDOG event), WDOG2 for ldo-bypass mode
(reset external pmic to trigger POR event).
For sl-evk board, there is no WDOG pin connected with external pmic as Sabresd
, because mx6sl boot at 400Mhz. Then both ldo-enable and ldo-bypass mode use
the common WDOG1 as reset source.
Robby Cai [Thu, 12 Sep 2013 06:39:57 +0000 (14:39 +0800)]
ENGR00279373 epdc: add GFP_KERNEL flag to make dma memory allocated from cma
Add GFP_KERNEL flag for dma_alloc_writecombine() and dma_alloc_coherent()
to make dma memory allocated via cma. Otherwise it's from dma pool whose
size is too small by default (256KB) and will cause allocation failure unless
use 'coherent_pool=xxM' in cmdline. We prefer cma now.
As we need to float DDR IO when entering DSM, so those registers
we need to access after DDR IO is floated must be contained in TLB,
otherwise, the TLB update may case DDR access and lead to
system hang. To make sure these registers' address is in TLB,
we need to flush TLB first then access them manually.
The following commit introduced a wrong sanity check for
the io_regulator which is intended to be got from device tree. a364635a535705a8c16df49ff9bc7b9362b083ec
Oliver Brown [Sun, 8 Sep 2013 20:05:28 +0000 (15:05 -0500)]
ENGR00278667-1 [mxc_v4l2_capture]: Add adv7180 driver in 3.10.9 Kernel
Copied file from 3.5.7 Kernel
commit de6459732a23402cbe520812bf4202299330fd68
Author: Oliver Brown <oliver.brown@freescale.com>
Date: Mon Jun 24 16:41:17 2013 -0500
Added missing call to clk_disable_unprepare() in adv7180_probe.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
-Added function and file name to some error messages that are
in multiple places.
-Added calls to clk_prepare_enable() and clk_disable_unprepare()
in ov5640_probe() to manage the sensor clock.
-Added missing sanity check for "io_regulator"
-Fixed several whitespace errors
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
We observed on some sd3.0 cards(Toshiba SDHC U1) that it may require
to reset host controller before sending the next tuning command
or the tuning may fail and cause the card can not work on uhs mode.
The root cause why the card fails on tuning without reset is still unknow.
This could be treated as a workaround before finding root cause.
ENGR00278646-8 mmc: sdhci-esdhc: correct pre_div for imx6q
According to spec, the pre_div for imx6q should be 1, or the biggest clock
rate we can get is a half of host clock rate.
This may cause we can not get the proper clock rate as we want.
e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too,
then it causes the actual clock we get is 100Mhz due to pre_div is 2.
ENGR00278646-6 sdhci: sdhci-esdhci-imx: add sd3.0 clock tuning support
Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from
the standard tuning process defined in host controller spec v3.0.
Thus we use platform_execute_tuning instead of standard sdhci tuning.
The main difference are:
1) not only generate Buffer Read Ready interrupt when tuning is performing.
It generates all other DATA interrupts like the normal data command.
2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW,
instead it's controlled by SW.
3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW,
it's controlled by SW.
4) the clock delay for every tuning is set by SW.
ENGR00278646-4 sdhci: sdhci-esdhc-imx: support real clock on and off for imx6q
The signal voltage switch follow requires to shutdown and output
clock in a specific sequence according to standard host controller
v3.0 spec. In that timing, the card must really receive clock or not.
However, for i.MX6Q, the uSDHC will not output clock even the clock
is enabled until there is command or data in transfer on the bus,
which will then cause singal voltage switch always to fail.
For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let
controller to gate off clock automatically and set that bit
to force clock output if clock is on.
ENGR00278646-3 mmc: sdhci-esdhci: move common esdhc_set_clock to platform driver
We need a lot of imx6 specific things into common esdhc_set_clock
for support SD3.0 and eMMC DDR mode which is not needed for power pc
platforms, so esdhc_set_clock seems not so common anymore.
Instead of keeping add platform specfics things into this common API,
we choose to move that code into platform driver itself to handle.
This can also exclude the dependency between imx and power pc on this
headfile and is easy for maintain in the future.
ENGR00278646-1 mmc: sdhci: add hooks for platform specific tuning
The tuning of some platforms may not follow the standard host control
spec v3.0, e.g. Freescale uSDHC on i.MX6Q/DL.
Add a hook here to allow execute platform specific tuning instead of
standard host controller tuning.
Robby Cai [Wed, 11 Sep 2013 05:27:59 +0000 (13:27 +0800)]
ENGR00279087-2 csi_v4l2_capture: move int_dev_init() to open function
By later initialization for camera dev (to call int_dev_init), the driver
works well whether the master (csi_v4l2_capture) or the slave (ov5640)
has been attached first. In this way, the driver can stick to the philosophy
for the V4L2_INT_DEVICE framework (the attach sequence shouldn't matter).
-Added function and file names to error messages that are similar
-Changed mxc_v4l_open to use clk_prepare_enable()
-Changed mxc_v4l_open to use clk_disable_unprepare()
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Copied mipi_csi.h from:
commit 50ca92f4010a93be265de7aad501b4dcae095a63
Author: Sheng Nan <b38800@freescale.com>
Date: Thu Mar 7 13:39:54 2013 +0800
ARM: include: remove definition of mipi-csi2 platform data
Other files copied files from:
commit 1fb93870965b7d8d67b4db6233a30c06d82f84fc
Author: Liu Ying <Ying.Liu@freescale.com>
Date: Thu Mar 21 12:15:52 2013 +0800
MIPI-CSI2:Fix a build warning
- Changed includes files for 3.10
- Dropped deprecated __devexit
- Added generic error message if probe fails
- Added configuration and set default to 'n'
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Oliver Brown [Sun, 8 Sep 2013 16:37:14 +0000 (11:37 -0500)]
ENGR00278683-1 [iMX6DLQ]: Add IOMUX configuration for IPU1 CSI0
Add IOMUX configuration for IPU1 CSI0 for SabreSD and SabreAuto. This
enables parallel CSI port required for OV564x on SabreSD and ADV7180
on SabreAuto.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
ENGR00278967 ASoC: fsl: Fix null pointer when rmmod snd-soc-imx-hdmi
When rmmod snd-soc-imx-hdmi if loadable module feature of HDMI audio
is being used, there would be a kernel dump promt:
Unable to handle kernel NULL pointer dereference at virtual address
This was caused by inappropriate priv pointer fetching, thus fix it.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig:
"In some older versions of glibc [<=2.8] SWP is used during futex trylock()
operations with the assumption that the code will not be preempted. This
invalid assumption may be more likely to fail with SWP emulation enabled,
leading to deadlock of the user application."
The audio codec toolchain version is gcc-4.1.1-glibc-2.4, we need turn off
the CONFIG_SWP_EMULATE in the imx_v7_defconfig.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
ENGR00277382-2 [MX6SL] Add WaIT mode support for MX6SL.
Enable WAIT mode support for MX6SL. Need to ensure that the
ARM:IPG clock ratio is maintained at 12:5 when WFI is executed.
This is the fix for the WAIT mode issue on MX6SL.
Set AHB to 132Mhz at boot, which is the recommended freq for AHB.
ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.
Need to ensure that PLL1 and PLL2 have the enabled bit set even when
the PLL is powered down and disabled.
1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled.
2. PLL2 will be set to bypass and enabled state (can be powered down) in low
power IDLE mode.
ENGR00269945: ARM: imx6: add the secondary sabreauto dts for pin conflict
The patch is to solve the pin conflicts between devices that are
currently added in imx6qdl-sabreauto dts file. It has ecspi1, i2c3, and
uart3 enabled while gpmi and weim disabled in the primary
imx6qdl-sabreauto.dtsi, and creates the secondary
imx6q/dl-sabreauto dts to have gpmi and weim enabled while others
disabled. Since usbh1 and usbotg depend on GPIO from max7310 on i2c3,
they have to be disabled as well in the secondary sabreauto dts files.
It's basically a revert of commit fc52e42 (ENGR00269945: ARM: imx6:
remove sabresd hdcp dts files).
As we agree that maintaining multiple dts files for internal tree should
not be a problem, let's add the hdcp dts files back as the solution to
hdcp pin conflict.
Jason Liu [Thu, 5 Sep 2013 23:36:10 +0000 (07:36 +0800)]
ENGR00278489 imx: i.mx6d/q: disable the double linefill feature of PL310
The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
But according to ARM PL310 errata: 752271
ID: 752271: Double linefill feature can cause data corruption
Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
Workaround: The only workaround to this erratum is to disable the
double linefill feature. This is the default behavior.
without this patch, you will meet the following error when run the
memtester application at: http://pyropus.ca/software/memtester/
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668.
FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678.
FAILURE: 0x00100000 != 0x00200000 at offset 0x0136567c.
Robby Cai [Tue, 3 Sep 2013 09:42:22 +0000 (17:42 +0800)]
ENGR00275034-5 ARM: imx_v7_defconfig: enable camera and v4l2 capture support
Enable the following options on imx6sl
CONFIG_VIDEO_V4L2_INT_DEVICE=y
CONFIG_VIDEO_MXC_CAPTURE=y
CONFIG_VIDEO_MXC_CSI_CAMERA=y
CONFIG_MXC_CAMERA_OV5640=y
This patch also does
- use module_i2c_driver() instead of module_init/exit.
- set the regulator reference pointer to NULL if it's not found in DT.
Otherwise call regulator_enable/disable() on it will cause dump
since the codes only check the regulator against NULL before the call
and it's not NULL but still invalid.
- drop gpo regulator definition and operations since it's of no use
projects / karo-tx-linux.git / log