ENGR00142679 SCC2 and SAHARA: changes to support loadable modules
To allow SCC2 and SAHARA drivers to work as loadable modules, needed
to add GPL license to SAHARA driver, export a couple of functions
from SCC2 driver, and the following data buffer mapping change in
SAHARA driver:
When compiled as a loadable module, a data buffer to be DMA'ed in the
SAHARA driver may not be in the kernel direct-mapped region but in
the "Kernel module space" between TASK_SIZE and high_memory-1
(see http://www.arm.linux.org.uk/developer/memory.txt). In this
scenario, the driver canno simply use the __pa macro to obtain
the physical address. It must walk the page tables to find the
page and use the page_to_phys function to find the physical
address that corresponds to the data buffer.
Jason Chen [Thu, 28 Apr 2011 03:23:36 +0000 (11:23 +0800)]
ENGR00141552 ipuv3: fix display pin's power leak
If you disable display, the display port's pin may keep high voltage which
may cause power leakage. Fix this issue by make all pin go into low level
after display disable.
Jason Chen [Tue, 19 Apr 2011 08:33:28 +0000 (16:33 +0800)]
ENGR00141152-1 header file: make default display option
After this patch, default display for below platforms:
mx51 bbg: DVI-XGA on DI0
mx53 ard: LVDS-XGA on DI0
mx53 evk: CLAA-WVGA on DI0
mx53 loco: VGA-XGA on DI1
mx53 smd: LVDS-XGA on DI1
The default options will work if you do not enter other video cmdline options.
For platform need enable other drivers, it will enable it automatically.
For example, under default option, mx53 loco will enable tve-vga driver
automatically; before this patch, it need add 'vga' to cmdline to enable it.
And 'di1_primary' option also will be enabled automatically if need.
If you want to overwrite the default option, please refer to below:
Zhou, Jie [Wed, 2 Mar 2011 17:02:40 +0000 (01:02 +0800)]
ENGR00140050 GPU: workaround hang with heavy bus loading
The GPU hang when run two cubes together with one video playback.
According to the suggestion from AMD, we'd better not read register
when GPU active, especially for CP block.
ENGR00142296-2 SRTC: Upgrade driver to kernel version 2.6.38
RTC-DEV ioctl interface changed, which required a definition
of new callback mxc_rtc_alarm_irq_enable in SRTC driver.
Also, added a sync call to mxc_rtc_interrupt after a write to
LP domain register to make sure we wait 3 clock cycles in order
for the write to complete, as required by the hardware.
ENGR00142089-3 MX51/MX53: Upgrade SCC2 and SAHARA drivers to 2.6.38
Starting with 2.6.36, ioctl file operation is removed; therefore,
changed ioctl function to unlocked_ioctl function, which has a
different function prototype and requires local locking mechanism
to prevent more than 1 user from accessing ioctls at the same time.
Modified SCC2 driver to obtain IRQs from resource array.
Modified SAHARA driver to use either MX53 or MX51 base address and
irq definitions since the generic versions are no longer defined
in the machine layer header files.
Jason Chen [Fri, 15 Apr 2011 08:25:57 +0000 (16:25 +0800)]
ENGR00141363 ARM imx53 clock: change di0 clock default parent to pll3
If enable both LVDS and one display device use external di clock, there will
be conflict between their clock parent -- both use pll4 on mx53. So it need
change di0 clock parent to pll3, and then uart parent need change to pll2 to
avoid console mess.
Jason Chen [Wed, 23 Feb 2011 10:18:50 +0000 (18:18 +0800)]
ENGR00139635 mxc edid: add edid name sysnode
Add name sysnode to mxc_ddc and sii902x, which can be check under:
/sys/devices/platform/mxc_ddc.0/fb_name
or
/sys/devices/platform/sii902x.0/fb_name
It's the name of fb fix id which it associated.
Tony Lin [Tue, 11 Jan 2011 10:01:03 +0000 (18:01 +0800)]
ENGR00137979-1 add performance monitor driver
add performance monitor driver.
sample:
cd /sys/devices/platform/mxs-perfmon.0/
'echo 1 > MIDn-xxx' to enable monitor this channel
n: channel number; xxx: name of channel (PXP, LCD...)
you can enable the multiple channels you want to
monitor respectively using this command.
use following command to check the channel is enabled
'cat MIDn-xxx'
1: enable; 0: disable
'echo read > Monitor' to monitor all read activities
'echo start > Monitor' to start monitoring
'echo fetch > Monitor' to get a snapshot of monitor statistics.
'cat xxx_Count' to show the statistics.
xxx: name of statistics, (Data, Transfer, Latency...)
'echo clear > Monitor' to clear snapshot of monitor statistics.
'echo stop > Monitor' to stop monitoring
- Removed setting of pfd_disable_mask bits in pfd enable/disable functions.
This feature, which automates the disabling of the APLL, was being used
incorrectly and is less clear than manually enabling/disabling PFD and
APLL clocks directly.
- Added wait for APLL relocking after APLL is enabled.
Peter Chen [Tue, 22 Mar 2011 09:27:17 +0000 (17:27 +0800)]
ENGR00140950 mfg: fix the bug that ubiformat utility breaks utp protocol
ubiformat includes command, data, command periods,
it breaks utp protocol for PUT commands. So we add two operations to fix it.
One is sending busy to host before the data periods begins.
The second is adding a new command to waiting ubiformat's command period.
Signed-off-by: Li Xingyu <b02754@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Jason Liu [Tue, 12 Apr 2011 06:24:00 +0000 (14:24 +0800)]
ENGR00141977 MX50: Kernel can't boot up
Kernel can't boot up on 2.6.38 branch due to the that
Russell has made one change to MT_HIGH_VECTORS, which
result in this memory region is read-only, so, memcpy
will fail when copy suspend code into iram.
Since the iram code region need excuting and rw attribue,
change the MT_HIGH_VECTORS to MT_MEMORY.
ENGR00122019 SAHARA: Add padding around buffers to prevent cache incoherency
Added padding of 64 bytes (cache line size for Cortex-A8) around
buffers that are used by the hardware to prevent any cache
coherency problems that could arise if buffers share a cache line
with some other data that is used by the CPU.
ENGR00141478-2 SAHARA: Move header file to include directory
The user mode libsahara library relied on header file
drivers/mxc/security/sahara2/include/sahara.h. However, to make
the lib build after headers_install step and to remove dependency on
kernel source, moved this header to include/linux/mxc_sahara.h.
These changes are specific to the include/linux folder.
ENGR00141478-1 SAHARA: Move header file to include directory
The user mode libsahara library relied on header file
drivers/mxc/security/sahara2/include/sahara.h. However, to make
the lib build after headers_install step and to remove dependency on
kernel source, moved this header to include/linux/mxc_sahara.h.
These are the necessary changes in the SAHARA driver to use the new
header file in the new location.
Liu Ying [Tue, 8 Mar 2011 06:59:21 +0000 (14:59 +0800)]
ENGR00140391 ISL29023:Keep int thresholds in interrupt handler
We used to set the interrupt thresholds to the measure range
of the light sensor in the interrupt handler, this potentially
makes user poll on the input event and never be waken up.
This patch keeps the interrupt thresholds in the interrupt
handler and is tested on MX53 SMD.
Liu Ying [Tue, 22 Feb 2011 09:11:30 +0000 (17:11 +0800)]
ENGR00139383-2 Add ISL29023 light sensor support
This patch adds ISL29023 light sensor support.
Users may control the light sensor work at
different modes/ranges/resolutions or read
the lux value via sysfs.
A power state node is also created in sysfs.
If the light sensor works at ALS once mode,
users need to power down/power up the sensor
before read the lux value again.
Currently, IR(Infra Red) mode is not supported.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
ENGR00141647 AUDIO,SGTL5000: Fix codec error after reset
sgtl5000 codec not work after board reset, this is caused by
sgtl5000 using register address step is 2, and snd-soc-core can't
handle this as we expect, so we have to fill the register cache by
reading register out when initialization instead of providing a default
value array.
Huang Shijie [Mon, 30 Aug 2010 01:51:18 +0000 (09:51 +0800)]
ENGR00141399-5 OCOTP: add the ocotp driver
Add a new driver for On-Chip OTP controller. The driver
will register all the register names of all the banks to /sys/.
You can use the following commands to manipulate the OTP banks:
Richard Zhao [Tue, 22 Mar 2011 02:22:15 +0000 (10:22 +0800)]
ENGR00141399-2 iMX5x: add clock debug information
Expose clock debug information to debugfs, which makes it easier for clock
system debug by using tools like powerdebug developed by Linaro power
management group.
For long term, this can go into common clock framework, but so far it depends
on the process of common clk API development. Once the common clk API is
ready in upstream, the clock debug information will be based on it too.
The implementation based on common clk API had also been finished and
reviewed with Jeremy.
ARM: iMX5x: fix clock debug enable_count error
Signed-off-by: Yong Shen <yong.shen@linaro.org> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com>
projects / karo-tx-linux.git / log