ENGR00215182-2 MXC HDMI CEC: Add basic support for HDMI CEC
- Add MXC HDMI CEC to kconfig and makefile under driver/mxc
- Add initial mxc_hdmi-cec.c file to provide basic HDMI CEC
functionality:
- Basic HDMI CEC resource initilize functional
- Support for sending and receiving CEC message via CEC line
- Report HDMI cable status to CEC lib at userspace. Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
ENGR00215182-1 sabresd: Add basic support for HDMI CEC
- Changes to IOMUX to allow HDMI CEC controller to use KEY_ROW2
pin that it needs
- Add cec device in platform-mxc_hdmi.c
- Add MXC_HDMI_CEC in imx6_defconfig
Steve Cornelius [Sat, 30 Jun 2012 23:11:00 +0000 (16:11 -0700)]
ENGR00215492-3: Detect HW features during alg registration
i.MX6 instantiates a CAAM with a low-power MDHA block, which does not
compute digests larger than 256 bits. Since the driver installs handlers
for hashes longer than 256 bits in several places, added the ability to
read and interpret the CHA version and instantiations registers, and then
only register handlers that it can support.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
If no platform_data ,the pdata will be NULL.If the driver try to access the
pdata->platform_set_disconnect_det,dump will occor.SO we should check the
pdata is NULL before checking pdata->platform_set_disconnect_det.
ENGR00215491 [MX6]Need to increase BUS freq when CPU freq is increased
When BUS freq is running at DLL off mode(24M or 50M), when CPU
freq is increased, we need to increase BUS freq to 400M setpoint
in order to achieve high performance when CPU is busy.
Robin Gong [Mon, 2 Jul 2012 02:41:57 +0000 (10:41 +0800)]
ENGR00215489-1 WDOG:add WDIOC_SETPRETIMEOUT and WDIOC_GETPRETIMEOUT interface
Add these two interface, so than user can set and get pre-timeout value to save
some important data before watchdog reboot. Signed-off-by: Robin Gong <B38343@freescale.com>
Richard Liu [Mon, 2 Jul 2012 01:34:31 +0000 (09:34 +0800)]
ENGR00215344 GPU became slow after long time run some applications
GPU became slow after long time run some applications
root cause is when GPU reserved memory exhaust, GPU will request continue physical
memory which will trigger defregment operation in kernel and cause system slow
Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Lily Zhang
Sandor Yu [Fri, 29 Jun 2012 10:18:55 +0000 (18:18 +0800)]
ENGR00215340 HDMI PHY config adjust to pass electrical compliance test
In the HDMI PHY internal, there are two register that can adjust
waveform of eyediagram.
0x0e -- voltage level control; it can adjust the single end data signals;
0x09 -- define pre-emphasis factor;
(it will affect the rise time and fall time of D0/D1/D2);
Adjust HDMI PHY register 0x09 and 0xe for MX6DL SabreSD and MX6Q SabreSD
waveform of eyediagram to pass HDMI compliance test electrical test case.
Liu Ying [Wed, 27 Jun 2012 08:08:49 +0000 (16:08 +0800)]
ENGR00215041-2 MX6 SabreSD:Set clko parent to be clko2
On MX6 SabreSD board, gpio_0 is muxed to clko to be
audio mclk and camera mclk. 24MHz osc clk is a stable
clock source, which can meet the requirement of audio
mclk and camera mclk. This patch sets clko parent
clock to be clko2 clock so that camera mclk and audio
mclk can source from osc clk.
There are 2 benifits after applying this patch:
1) clko's original parent clock(pll4_audio_main_clk)
can be gated off to save power or used by another
module.
2) ov5640/ov5642 camera most settings can reach
claimed 15fps or 30fps with no human eye recognizable
video quality downgrade.
Lin Fuzhen [Thu, 28 Jun 2012 06:54:36 +0000 (14:54 +0800)]
ENGR00215195 MX6 PM:Add necessary info for waitmode to help debug system issue
Add debug message for wait mode to check it was enabled or not.
it will easy to get the wait mode status from this info
e.g, if wait mode is enabled, there are below info from console:
wait mode is enabled for i.MX6
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
Steve Cornelius [Thu, 28 Jun 2012 22:27:16 +0000 (15:27 -0700)]
ENGR00215228-12: Move scatter/gather cache coherence into chained function.
Last driver revisions began to incorporate optimized mapping functions
for scatter/gather list management, and then centralized them as inlinable
functions usable from multiple modules. Since these became more globally
useful, moved the coupled cache-coherence functions out of the mainline code
and into the inlined ones for simplification.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Tue, 26 Jun 2012 01:19:09 +0000 (18:19 -0700)]
ENGR00215228-11: Enable ahash and rng configurations
Add in ahash and rng options for build. Note that because of the way
platform devices detect (as opposed to of-based detection), modularization
of API interfaces is suppressed. Once CONFIG_OF is possible, this
can go away.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Tue, 26 Jun 2012 00:51:58 +0000 (17:51 -0700)]
ENGR00215228-9: Add hash and RNG initializers for non-OF builds
Inserted explicit initializers for split-out startup and shutdown functions
needed for kernels using platform devices in place of OF-device-tree
initialization and detection.
Also added necessary ahash algorithm list head to driver private storage
block.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Fri, 22 Jun 2012 23:32:08 +0000 (16:32 -0700)]
ENGR00215228-6: Externalize scatter-gather handling for multiple API modules.
Moved scatter-gather list management outside of single API module
in anticipation of multiple API modules which may be switch selectable.
This includes a number of list management optimizations, as well as
some aead descriptor optimizations.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Fri, 22 Jun 2012 23:13:53 +0000 (16:13 -0700)]
ENGR00215228-4: Synchronize scatter/gather table definitions with QorIQ defs
Update scatter/gather definitions to more closely correspond with
those in the QorIQ 1.2 release tree. Note that the definition of
the CAAM-local scatter-gather table for QorIQ/Power-based devices
assumed big-endian, and therefore does not burst-read properly into
an ARM-based little-endian instantiation. Therefore, applied
close-as-practical definitions to at least get close until a merge
can be accomplished.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Robin Gong [Thu, 28 Jun 2012 06:24:40 +0000 (14:24 +0800)]
ENGR00215188-2 LDO bypass: disable LDO bypass before suspend and back in resume
There is one SOC bug if use LDO bypass, VDDARM_CAP will take 2ms to raise up
normal voltage when system resume back, longer than 40us before. Then it will
cause cpu hang if resume back.
Workaround:
We can disable LDO bypass at the last minute of suspend and enable LDO bypass
again as long as system resume back. Signed-off-by: Robin Gong <B38343@freescale.com>
Robin Gong [Thu, 28 Jun 2012 06:14:46 +0000 (14:14 +0800)]
ENGR00215188-1 PFUZE CPUFREQ: reconstruct LDO bypass function
As before, raw I2C operation is added in suspend interface of cpufeq driver,so
that we can raise up cpu frequency and voltage after I2C driver suspended.But
the code is not platform independent if customer use another pmic whose I2C
slave address is different with pfuze.
Now, we rasie up cpu frequency and disable cpu frequency change in more earlier
than before. If system begin to suspend flow, we will do this. Signed-off-by: Robin Gong <B38343@freescale.com>
Francisco Munoz [Tue, 12 Jun 2012 19:59:31 +0000 (14:59 -0500)]
ENGR00213293 : Enable WEIM NOR support on the imx6 ARD revb quad/solo.
Added IOMUX,GPIO and early param support for the parallel nor to work
on the imx6 revB quad/solo. Since the parallel NOR can clash with I2C3,
and SPI, an early param was added to enable WEIM NOR chips using boot
args.
The Weim NOR needs a HW rework for it to work. This rework is going
to disable the SPI NOR. Modified files:
Eric Sun [Mon, 25 Jun 2012 11:03:46 +0000 (19:03 +0800)]
ENGR00214813 MX6DL SabreSD : Kernel, Enable ARM Perfromance Monitor
Register PMU resources during system bootup, so that "Perf" Command can
be used to get misc performance data of a running program
The "Perf" Exe should be built manually in
"./tools/perf" using the following command line
> make CROSS_COMPILER=... ARCH=arm CFLAGS="-static -DGElf_Nhdr=Elf32_Nhdr"
then copy the "Perf" executable to rootfs/bin
Usage :
perf # show help content
perf list # show all available statistics options
perf stat ls # show all statistics of a "ls" command
perf stat -e cycles tar cvfz bin.tgz /bin
# show "cycles" statistics of command
# "tar cvfz ...."
MX6 Series Chips bound all CPUs PERFMON IRQ to one, this may cause some
problems when get per-CPU statistics. Need further investigation
Liu Ying [Tue, 26 Jun 2012 04:45:05 +0000 (12:45 +0800)]
ENGR00214865 mxc_v4l2_capture:Be silent when closing device
This patch changes the debug level of a kernel message in
mxc_v4l2_close() from KERN_INFO to KERN_DEBUG to make the
console silent when closing device.
Fugang Duan [Thu, 21 Jun 2012 08:28:57 +0000 (16:28 +0800)]
ENGR00210654 - MSL : fix NFS boot fails issue in sometime
- MX6 sololite cpu board NFS boot fails in sometimes, because MAC
cannot get any packets while sending DHCP to require IP. The
reproduce rate is 10%.
- Lan8720 phy enter a unexpected status, and need software reset
phy before transmition.
- Do some below overnight tests after add the changes, no NFS
boot issue found.
1. Kernel boot from MMC, rootfs mount from NFS.
2. Kernel boot from tftp, rootfs mount form NFS.
Ryan QIAN [Thu, 21 Jun 2012 06:40:40 +0000 (14:40 +0800)]
ENGR00213944-02: mmc: sdhci: [MX6] support SD v3.0 memory cards.
- Add variable pad speed setting per SD clk freq.
- Add SD3.0 support on SD1, SD2, and SD3.
- Enhance drive strength on SD pad to improve its compatibility.
- change the definition of pad speed changing interface
- combine pad speed setting for different SD host controllers into one function.
Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Lily Zhang
Ryan QIAN [Mon, 18 Jun 2012 22:56:24 +0000 (06:56 +0800)]
ENGR00213944-01: mmc: sdhci: support SD v3.0 memory cards.
- Correct switcing signaling voltage sequence according to SD3.0 spec,
that turn off SD clk before switching signaling voltage.
- previous code can work on MX6Q but failed on MX6SL.
- only have sequence corrected, it can work on MX6SL.
Wayne Zou [Wed, 20 Jun 2012 04:55:13 +0000 (12:55 +0800)]
ENGR00214337 MX6: Enable AXI cache for VDOA/VPU/IPU and set IPU high priority
set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Also, clear OCRAM_CTL bits to disable OCRAM read/write pipeline control.
Nancy Chen [Tue, 19 Jun 2012 22:21:43 +0000 (17:21 -0500)]
ENGR00212633 [MX6SL]: Add support for SoC power optimization in Idle mode
Add support for SoC power optimization in Idle mode (1st phase):
1. ARM @ 198MHz. VDDARM_CAP @ 0.85V
2. AHB @ 24MHz, DDR @ 25MHz
3. PU regulator disabled when system is in IDLE.
Terry Lv [Fri, 15 Jun 2012 04:38:11 +0000 (12:38 +0800)]
ENGR00213726: CAAM: Amend crypto API configuration for caam operation
Previous configuration suppressed a number of crypto API features that
caused misleading results when using the CAAM driver through the tcrypt.
Enabling the API tests eliminated this.
Also, added in other common ciphers and modes that, if lacking, would
cause confusion with tcrypt behavior.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Anson Huang [Tue, 19 Jun 2012 10:23:10 +0000 (18:23 +0800)]
ENGR00214199 [MX6]Need to lower ipg_perclk to 6M before init GPT
As Arik TO1.0 GPT use ipg_perclk as clock source, we need to
lower it to 6M before init GPT, or the clock source freq will
be wrong if we lower the ipg_perclk after GPT time already init.
Rong Dian [Fri, 15 Jun 2012 04:33:58 +0000 (12:33 +0800)]
ENGR00213722:MX6 SABRESD battery:add voltage offset sysfs
interface and modify driver
1.add battery sample voltage offset sysfs interface.
2.add usb charger powersupply from max8903 UOK.
3.modify battery max coulomb data to 99% in charger full stage and
modify battery max coulomb data to 100% in discharger stage,because
hardware cannot support battery internal resistance and coulomb
calculation.Battery voltage and coulomb may increase a bit in charger
stage,so keep max coulomb data 99% in charger full stage.
Robby Cai [Mon, 18 Jun 2012 11:46:41 +0000 (19:46 +0800)]
ENGR00213997: Fix Section Mismatch warning
Fix:
WARNING: vmlinux.o(.data+0x8c28): Section mismatch in reference from the
variable mx6_gpmi_nand_platform_data to the function
.init.text:gpmi_nand_platform_init()
The variable mx6_gpmi_nand_platform_data references
the function __init gpmi_nand_platform_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Robby Cai [Mon, 18 Jun 2012 05:14:08 +0000 (13:14 +0800)]
ENGR00213751: imx6sl: Add ELAN touchscreen support on EINK-DC3 board
Add ELAN capacitive TS support on EINK-DC3 stacked on MX6SL_ARM2 board
- configure the iomux setting (need 4.7K Ohm pull up on 'touch_int_b')
- configure the i2c slave addr
- configure the GPIO setting for ELAN ce/int/rst
- update the defconfig
Robby Cai [Tue, 12 Jun 2012 10:24:54 +0000 (18:24 +0800)]
ENGR00213749: imx6sl: Add keypad support on EINK-DC3 board
Add the support for keypad on EINK-DC3 board which is stacked on ARM2 board.
- configure the iomux setting
- add dummy kpp clock to fool imx_keypad driver
- add platform device for keypad
- add key mapping (4x4 array) used on EINK-DC3
- update the defconfig for keypad driver
Chen Liangjun [Mon, 11 Jun 2012 07:08:18 +0000 (15:08 +0800)]
ENGR00212318 ASRC:update to in/out width config
The origin ASRC driver did not support input and output wordwidth
config but an total wordwidth config instead. And the input wordwith
and output wordwidth are all fixed to 24 bit.
In this path, we do things below:
1 Update to use input wordwidth and output wordwidth config seperately
instead of an total wordwidth config.
2 Set corresponding DMA(input/output) buswidth according ASRC's input
and output wordwidth config.
3 Support 16/24 bit input wordwidth and 24 bit output wordwidth.
Anson Huang [Thu, 14 Jun 2012 10:07:30 +0000 (18:07 +0800)]
ENGR00212720 [MX6]Adjust CPU 672M setpoint voltage
Previous voltage for 672M is 1.05V, normal test is OK,
but if CPU is busy in background and do the CPUFreq change
as well, always fail the stress test at 672M setpoint, after
increase it to 1.1V, stress test is OK.
Wayne Zou [Tue, 12 Jun 2012 06:52:21 +0000 (14:52 +0800)]
ENGR00213158-3 FB: Clean up fb interrupt handler
Clean up the fb driver for maintainability:
1. Use completion instead of semaphore API interface.
2. Use IPU oneshot interrupt mode and remove ipu_disable_irq()
function call in interrupt handler.
Larry Li [Tue, 12 Jun 2012 09:11:45 +0000 (17:11 +0800)]
ENGR00213170-2 [MX6SL] Enable GPU driver
Use allocated GPU resource to enable GPU.
Memroy address on imx6sl board starts from 0x80000000
and GC320 can access [baseAddress, baseAddress + 2G) only without MMU.
So to make GC320 work, baseAddres must be set to 0x80000000, and all
address sent to GC320 must be a offset to baseAddress. GC355 doesn't
need this baseAddress, that means it needs a real physcial adress,
rather than the offset to baseAddress.
Original code always change phsysical address to 'offset' before use it,
no matter it is used by GC355 or GC320, so only one of them can work.
Solution is to move address adjustion to arch specific part. So each
core can get what it wants.
Signed-off-by: Larry Li <b20787@freescale.com> Acked-by: Lily Zhang
Anson Huang [Wed, 13 Jun 2012 12:20:01 +0000 (20:20 +0800)]
ENGR00180919 [MX6]Update clock tree if BUS freq is changed
As DDR freq change is by modifying CCM register directly,
we need to update the clock tree as well, or the clock
tree will be broken. Also, we need to make sure the clock
rate counting is right.
Robin Gong [Wed, 13 Jun 2012 06:44:00 +0000 (14:44 +0800)]
ENGR00213336 sabresd pfuze: support 1.2G by param which pass by u-boot
There is no fuse data for distinguish 1.2G or 1G, kernel need support passed
param from u-boot that can know 1.2G or 1G. If 1.2G, will configure VDDSOC_IN
&VDDARM_IN to 1.425V by pfuze and VDDSOC&VDDPU to 1.25V by internal ldo
Sandor Yu [Wed, 13 Jun 2012 11:18:43 +0000 (19:18 +0800)]
ENGR00180937 IPU: Change IPU error message to IPU warning
IPU driver will print unexpect interrupt state in ipu_irq_handler function,
It is for IPU debug and state check, not a IPU error.
So change print function from dev_error to dev_warn.
Anson Huang [Tue, 12 Jun 2012 10:50:42 +0000 (18:50 +0800)]
ENGR00180930 [MX6]Fix low bus mode bug when there is no CPUFreq change
If the CPUFreq change is done before enabling low bus freq driver,
the bus freq will be staying at high freq until there is new request
of entering low bus freq. So we need to put the bus freq into low
point if all the conditions are met when we enable bus freq.
projects / karo-tx-linux.git / log