Adrian Alonso [Sat, 17 Dec 2011 01:22:08 +0000 (19:22 -0600)]
ENGR00170523 imx6q-ard: add egalax touchscreen support
* Add egalax touch screen support for sabreauto platform
* Add egalax client to correct i2c channel
* Fix GPIO assigned to touch screen interrupt
* egalax driver depends of LED_CLASS for gpio interrupt handling
and HIDRAW for X11 event notification and added to mx6q_defconfig
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Huang Shijie [Fri, 16 Dec 2011 08:27:03 +0000 (16:27 +0800)]
ENGR00170465-1 MX6Q/SDMA : update the SDMA script for UART RX
The old script does not clear the IDLE flag.
So when the IDDMAEN(UCR4[6]) is enabled, the RX only receives few
bytes(such as 2 or 1 byte) per DMA operation.
Alan Tull [Thu, 8 Dec 2011 19:43:42 +0000 (13:43 -0600)]
ENGR00169872-2 rework hdmi initialization and hotplug sequence
This commit intends to implement the flowchart and details
documented in the HDMI Transmitter Controller User Guide
section entitled "Programming Model".
Some input is also from the Synopsys API code.
The HDMI specification requires HDMI to set itself to VGA DVI mode
before reading the EDID.
So follow this sequence when HDMI is hotplugged:
1. Hdmi connector is plugged in, HDMI video gets an interrupt.
2. Clear out video mode list. Add only VGA DVI mode to list.
3. Request VGA DVI mode (call fb_set_var())
4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
call mxc_hdmi_setup() to set up HDMI.
5. Read the edid and add video modes from edid. Select the video
mode that is similar to the command line default.
6. Request VGA DVI mode (call fb_set_var())
7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
do mxc_hdmi_setup().
Also included is a workaround for an overflow condition in the HDMI.
The frame composer has an arithmetic unit that gets updated every time
we write to one of the FC registers. But sometimes, depending on the
relation between the tmds and sfr clocks, it may happen that this unit
doesn't get updated, even though the registers are holding correct
values. The workaround for this is, after completing the controller
configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF)
three or four times with the same value, and then follow it up by a SW
reset to the TMDS clock domain (MC_SWRSTZ).
We clear the overflow condition as described above every time we
change video mode. Also an overflow interupt handler will clear the
overflow condition if it happens again. This overflow condition is
expected (and not a problem) when we are in DVI (non-HDMI) mode, so
we do not worry about it in that case.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
Alan Tull [Thu, 8 Dec 2011 19:43:42 +0000 (13:43 -0600)]
ENGR00169872-1 rework hdmi initialization and hotplug sequence
This commit intends to implement the flowchart and details
documented in the HDMI Transmitter Controller User Guide
section entitled "Programming Model".
Some input is also from the Synopsys API code.
The HDMI specification requires HDMI to set itself to VGA DVI mode
before reading the EDID.
So follow this sequence when HDMI is hotplugged:
1. Hdmi connector is plugged in, HDMI video gets an interrupt.
2. Clear out video mode list. Add only VGA DVI mode to list.
3. Request VGA DVI mode (call fb_set_var())
4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
call mxc_hdmi_setup() to set up HDMI.
5. Read the edid and add video modes from edid. Select the video
mode that is similar to the command line default.
6. Request VGA DVI mode (call fb_set_var())
7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
do mxc_hdmi_setup().
Also included is a workaround for an overflow condition in the HDMI.
The frame composer has an arithmetic unit that gets updated every time
we write to one of the FC registers. But sometimes, depending on the
relation between the tmds and sfr clocks, it may happen that this unit
doesn't get updated, even though the registers are holding correct
values. The workaround for this is, after completing the controller
configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF)
three or four times with the same value, and then follow it up by a SW
reset to the TMDS clock domain (MC_SWRSTZ).
We clear the overflow condition as described above every time we
change video mode. Also an overflow interupt handler will clear the
overflow condition if it happens again. This overflow condition is
expected (and not a problem) when we are in DVI (non-HDMI) mode, so
we do not worry about it in that case.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
Adrian Alonso [Fri, 9 Dec 2011 20:28:59 +0000 (14:28 -0600)]
ENGR00169975: imx6sabreauto fix i2c iomux pad settings
* imx6sareauto fix i2c iomux pad settings
* On sabreaauto the i2c pad settings are missing in iomux-mx6q.h
* update i2c pad seetings and SD2 control pads
* Set correct i2c address for io expanders (expander A and B)
* explicit assert io expander reset line for normal operation mode
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Felipe Balbi [Mon, 29 Aug 2011 08:54:08 +0000 (11:54 +0300)]
usb: gadget: audio: queue wLength-sized requests
On Audio class, the wLength field of the Setup
packet, contains the data payload size of the
following Data phase. Instead of harcoding values,
use wLength.
This also fixes a bug where Gadget driver had to
receive 3 bytes, but it was queueing a ZLP.
Felipe Balbi [Fri, 26 Aug 2011 09:48:15 +0000 (12:48 +0300)]
usb: gadget: audio: actually support both speeds
While testing g_audio with HighSpeed UDC on a
FS Hub, we had no configurations to present to
the host. That's because both speeds where
mutually exclusive.
In may gadgets bind and bind like functions were in a init section
as they were only run during initialisation. However, being
callback functions they were referenced from structures in “normal”
sections. Changing the tag from “__init” to “__ref” fixes the
warnings.
Signed-off-by: Michal Nazarewicz <m.nazarewicz@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Root cause is:
Ipu driver use msleep to wait for smfc idle, msleep isn't a
Accurate timer, but CSI SMFC is a real-time channel, so use
Interrupt handler to replace msleep.
wu guoxing [Fri, 16 Dec 2011 04:15:05 +0000 (12:15 +0800)]
ENGR00170452: gpu-viv: change from dma_sync_single_for_device to outer_clean_range
dma_sync_single_for_device can only used for kernel physical memory,
while in gpu, we will also clean user physical memory for pixmap,
direct texture, etc. outer_clean_range can operate on both.
ENGR00170212: MX6 - Implement a SW workaround for TKT065875
Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Adrian Alonso [Thu, 15 Dec 2011 01:24:18 +0000 (19:24 -0600)]
ENGR00170341 board-mx6q-sabreauto: update spdif for sabreauto platform
* Update spdif config options for sabreauto platform
* Correct pad settings
* Only SPDIF RX in sabreauto, unset SPDIF TX support.
* spdif and i2c3 doesn't conflict in sabreauto platform
remove spdif early param and logic that set either pads.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Jason Chen [Wed, 14 Dec 2011 06:09:08 +0000 (14:09 +0800)]
ENGR00170168-2 mxc_vout: add non FB_VMODE_YWRAP support
when use pan display, the case could be:
1. a small window wrap in a big frame buffer
2. a frame switch in a serial buffers
the ipuv3 fb driver used to support case 1, and for case 2,
if the fb format is interleaved, there is no problem, but for
non-interleaved format (like I420), there will be a display bug.
Jason Chen [Wed, 14 Dec 2011 06:02:16 +0000 (14:02 +0800)]
ENGR00170168-1 ipuv3 fb: add non FB_VMODE_YWRAP support
when use pan display, the case could be:
1. a small window wrap in a big frame buffer
2. a frame switch in a serial buffers
the ipuv3 fb driver used to support case 1, and for case 2,
if the fb format is interleaved, there is no problem, but for
non-interleaved format (like I420), there will be a display bug.
ENGR00170141: Fix debug messages generated by CPUFREQ
When dvfs-core is enabled along with "debug" in command line, CPUFREQ
printed too many debug messages.
Fix this by changing the threshold settings for DVFS-CORE and
make the transitions more conservative and infrequent.
Also use the CPUFREQ debug flag.
Xinyu Chen [Tue, 13 Dec 2011 07:29:59 +0000 (15:29 +0800)]
ENGR00170145-1 ipuv3: add resource for overlay fb buffer reservation
We have already had framebuffer reservation for BG display
by set the base/size resource in fb platform data.
But we may also have FG fb buffer reserve requirement.
So add addtional base/size resource in fb plaform data,
add a IORESROUCE_MEM resource when fb device register
to meet such requirement.
Xinyu Chen [Fri, 9 Dec 2011 06:47:57 +0000 (14:47 +0800)]
ENGR00169891 v4l2 capture: avoid streamon with only one buffer queued
If user space only queue one buffer into ready list, and
call streamon, camera csi enc ISR will crash.
Since for CSI ENC, the ping pong buffer is initilized without
checking ready buffer on streamon.
The second buffer will be wrongly in cam_data struct, and causes
DMA fill buffers into cam_data global variable.
Here just add one sanity check for ready buffer.
ENGR00163052: CPUFREQ does not report correct frequency
When DVFS_CORE is enabled, the following command reports incorrect frequency:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
Fix this by ensuring the CPUFREQ does not change the frequency
when DVFS_CORE is active. And DVFS-CORE informs CPUFREQ of the
change done to CPU frequency.
Tony LIU [Wed, 7 Dec 2011 05:31:35 +0000 (13:31 +0800)]
ENGR00169661:Remove the discharge for VBUS and DP
- VBUS discharge code should be removed from suspend_irq function
- On Arik, there is a huge capacitance(C86), even discharge VBUS,
the Drop of VBUS is still very slow
- On Arik, the B session valid threshold is not 0.8V or 1.4V, it is
about 2V~3V, so we can receive B session valid interrupt very soon
- No DP discharge needed, but wait for SE0 is needed Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Wayne Zou [Thu, 1 Dec 2011 11:52:39 +0000 (19:52 +0800)]
ENGR00163669-1 mxc fb: remove FB_EVENT_PREMODE_CHANGE for mxc fb drivers
remove FB_EVENT_PREMODE_CHANGE for mxc ldb/tve drivers
add dispdrv setup interface for ldb/tve drivers
re-structure the dispdrv framework for display devices
Xinyu Chen [Fri, 2 Dec 2011 06:38:21 +0000 (14:38 +0800)]
ENGR00163703 uart: console write routing is unsafe on SMP
The console feature's write routing is unsafe on SMP with
the startup/shutdown call. It happend to cause Android bootup
without shell runnable.
Actually on Android boot, there's 3 consumers of the console
* the kernel printk
* the init process using /dev/kmsg to call printk to show log
* shell, which open /dev/console and write with sys_write()
The shell goes into the normal uart open/write routing,
but the other two go into the console operations.
The open routing calls imx serial startup, which will write USR1/2
register without any lock and critical with imx_console_write call.
Here add spin_lock for startup/shutdown/console_write routing.
Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
as this will cause clock reinit, and output garbage.
Huang Shijie [Wed, 23 Nov 2011 08:45:17 +0000 (16:45 +0800)]
ENGR00163603-2 IMX/SDMA : save the real count for one DMA transaction.
When we use the SDMA in the UART driver(such as imx6q), we will
meet one situation:
Assume we set 64 bytes for the RX DMA buffer.
The receiving DMA buffer has received some data, but not full.
An Aging DMA request will be received by the SDMA controller if we enable the
IDDMAEN(UCR4[6]) in this case.
So the UART driver needs to know the count of the real received bytes,
and push them to upper layer.
Add two new fields to sdmac, and update the `residue` in sdma_tx_status().
Anson Huang [Thu, 1 Dec 2011 07:51:27 +0000 (15:51 +0800)]
ENGR00163275 [MX6]Fix PLL enable fail panic
The root cause is irqs come between PLL register reading
and getting system time, an interrupt handle could take
more than 2ms, which will make the time reading and register
reading unalignment, see below:
1. pll reg read, it is still not locked;
2. here comes an interrupt, and its handler could spent > 2ms;
3. time reading, found current time already > expiration time(1.2ms),
and we treated the pll lock fail;
There are two method could fix it, one is disable interrupt
during pll lock bit and time expiration check, the other is
to add a second time read after time expiration to make sure
the pll didn't lock during the time we set. I choose the seconde
choise, since it impacts kernel less than disable interrupt;
projects / karo-tx-linux.git / log