Anish Trivedi [Fri, 28 Oct 2011 18:07:00 +0000 (13:07 -0500)]
ENGR00161005-1 MX6Q Kernel Rename sabreauto to arm2 board
Machine layer patch.
Sabreauto is an inaccurate name for the Armadillo2 board that
this code is actually meant for. So, renamed "sabreauto" board file,
configs, and code to "arm2". Created a new machine id for
ARM2 board.
Alan Tull [Tue, 25 Oct 2011 20:41:55 +0000 (15:41 -0500)]
ENGR00160860-2 hdmi audio driver
Audio driver for i.Mx built-in HDMI Transmitter.
* Uses HDMI Transmitter's built-in DMA.
* Adds IEC958-style digital audio header info to the raw audio.
* Gets pixel clock from the IPU driver and calculates clock
regenerator values (cts and N).
* Move ipu_id, and disp_id from the HDMI's platform data to the
HDMI mfd's platform data. Saves them in the hdmi mfd.
* Add mfd functionality to update the clock regenerator values
when the hdmi changes the pixel clock rate or when requested
from the audio driver with a new audio sample rate.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
Alan Tull [Thu, 15 Sep 2011 20:51:33 +0000 (15:51 -0500)]
ENGR00160860-1 hdmi audio driver
Audio driver for i.Mx built-in HDMI Transmitter.
* Uses HDMI Transmitter's built-in DMA.
* Adds IEC958-style digital audio header info to the raw audio.
* Gets pixel clock from the IPU driver and calculates clock
regenerator values (cts and N).
* Move ipu_id, and disp_id from the HDMI's platform data to the
HDMI mfd's platform data. Saves them in the hdmi mfd.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
Anson Huang [Wed, 26 Oct 2011 03:14:34 +0000 (11:14 +0800)]
ENGR00160798 [MX6]Workaround for NFS
Disable SCU standby mode will prevent SOC enter
WAIT mode, so, by default, we would not enable
WAIT mode to make NFS work, to enable WAIT mode,
you should not use NFS, and pass "enable_wait_mode"
from uboot.
ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.
When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source
pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power.
Sammy He [Wed, 26 Oct 2011 12:46:39 +0000 (20:46 +0800)]
ENGR00160802-2 vpu: Check interrupt reason before disable clock
There may be more interrupt than PIC_DONE reported, we cannot disable
clock if picture isn't done since vpu is still in busy in the status.
This patch will check interrupt reason before clock is disabled.
Alan Tull [Wed, 26 Oct 2011 18:13:47 +0000 (13:13 -0500)]
ENGR00160862 unique id for each soc-audio device
On boards which have more than one soc-audio device, the initialization
of the first device will create a sysfs directory named
/sys/devices/platform/soc-audio and subsequent soc-audio devices will
fail to init because they try to create another sysfs directory of the
same name.
The solution is to have a unique number for each device such that
different boards having combinations will be OK.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
Huang Shijie [Wed, 26 Oct 2011 09:31:25 +0000 (17:31 +0800)]
ENGR00160834 UTP : replace kzalloc() with vmalloc()
When allocating large memory, such as 128K,
vmalloc() uses single page for the allocation process,
while kzalloc() has to consume a continuous pages for the allocation.
In low memory case, the kzalloc() may fails.
So use the vmalloc() instead.
Danny Nold [Mon, 24 Oct 2011 16:11:17 +0000 (11:11 -0500)]
ENGR00160692 - MXC HDMI: Unbalanced clk disable
HDMI IAHB clock was capable of being disabled twice consecutively
due to a race condition between enabling the HDMI interrupts
and disabling the HDMI clock. A spinlock has been added to protect
against the race condition.
Another race condition was present due to the driver handling
HPD (hotplug detect) and RX Sense interrupts separately. Only HPD
interrupts handled now, simplifying enable/disable flow and
eliminating the race condition.
One final race condition fixed during HDMI driver initialization.
IRQ request moved to after place where IAHB is disabled, to ensure
balanced enable/disable of IAHB clock.
Signed-off-by: Danny Nold <dannynold@freescale.com>
ENGR00160397: Fix build break caused by DVFS-CORE driver
loops_per_jiffy is a global variable for non-smp platforms.
For SMP platforms, loops_per_jiffy is a per_cpu variable.
Fix dvfs_core to adjust loops_per_jiffy for both configurations.
- Ensure HDMI clocks are disabled when leaving HDMI core probe function.
- Create HDMI core api to allow HDMI sub-drivers to init, enable, and
disable the HDMI IRQ. Required to optimally manage HDMI clocks,
allow IAHB to be disabled, and still have video and audio sub-drivers
able to receive interrupts.
- Update code to adjust for decoupled ISFR and IAHB clocks.
- Disable IAHB clocks whenever HDMI not plugged in.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Anson Huang [Tue, 11 Oct 2011 12:15:21 +0000 (20:15 +0800)]
ENGR00159796 [MX6]Cooling of cpufreq should consider governor type
We need to consider governor type of cpufreq, previous
method is to change the cpufreq to the lower point, but
it would not work if the cpufreq governor is not userspace,
now we set the scaling max freq instead of cpu current freq,
this will make sure working for all the governor.
Anson Huang [Tue, 11 Oct 2011 12:03:16 +0000 (20:03 +0800)]
ENGR00159737 [Mx6]Add clock check for periph clk
For lpddr2 board, current freq only support up to
400MHz, in this case, periph clk will set to 400M
in uboot, so in clock init, we need to check
whether the ddr clock is set to 400M, if yes, then
we should set periph clk parent to pll2_pfd_400M.
Anson Huang [Sun, 9 Oct 2011 01:47:20 +0000 (09:47 +0800)]
ENGR00156635 [MX6]Dormant random resume fail
1. sometimes system can not resume successfully from
dormant mode, there is still some defect with L2 cache
array alive during dromant mode, add clean operation
before dormant to make sure data alignment between L2
and DRAM, after doing it, dormant mode can resume fine.
2. local time no need to do store and restore during
suspend/resume.
Eric Miao [Mon, 26 Sep 2011 02:46:27 +0000 (10:46 +0800)]
SAUCE: set correct rates before registering SPDIF codec DAI
BugLink: http://bugs.launchpad.net/bugs/855281
Playback/capture rates should be configured before the SPDIF codec
DAI is registered, according to the parameters that passed in by
the platform data. And this caused pulseaudio not working with the
SPDIF sound card.
Add work around to the reboot issue of SMP, with
SMP, all the CPUs need to do _rcu_barrier, if we
enqueue an rcu callback, we need to make sure CPU
tick to stay alive until we take care of those by
completing the appropriate grace period.
This work around only work when the reboot command
issue, so it didn't impact normal kernel feature.
Danny Nold [Thu, 22 Sep 2011 21:43:24 +0000 (16:43 -0500)]
ENGR00157457 - MXC HDMI: Add support for non-CEA spec video modes
- Updated PHY configuration code to support ranges of clock frequencies,
rather than just a small set of supported clock frequencies corresponding
to CEA-861 video modes. This means that PC monitor modes are now
supported.
- Updated color handling code to ensure that a consistent set of
color mode defines are used.
- Fixed bug in how clock disable registers are configured
Signed-off-by: Danny Nold <dannynold@freescale.com>
Will Deacon [Wed, 20 Jul 2011 13:18:46 +0000 (14:18 +0100)]
ARM: twd: register clockevents device before enabling PPI
The smp_twd clockevents driver currently enables the local timer PPI
before the clockevents device is registered. This can lead to a kernel
panic if a spurious timer interrupt is generated before registration
has completed since the kernel will treat it as an IPI timer.
This patch moves the clockevents device registration before the IRQ
unmasking so that we can always handle timer interrupts once they can
occur.
Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Danny Nold [Thu, 8 Sep 2011 20:38:25 +0000 (15:38 -0500)]
ENGR00156300 - EPDC fb: Move ISR code to work Q & replace spinlocks with mutexes
- Move the majority of code from the IRQ handler routine into a workqueue
routine. This should improve system interrupt latency.
- Change the spin_lock protecting EPDC queues into a mutex and change all
associated spin_lock calls into mutex calls.
Signed-off-by: Danny Nold <dannynold@freescale.com>
We can leave L2 cache alone during dormant,
just keep in mind don't access cache in dormant
process, then it should be OK without flushing
L2 cache, it will improve performance of suspend
and resume.
Jason Chen [Tue, 6 Sep 2011 06:06:09 +0000 (14:06 +0800)]
ENGR00155146 ipuv3: use mutex instead of spin lock
keep spin lock for irq function, but use mutex replace other
splin lock to provide better sync method.
Add _ipu_get/put function to check clock enable.