Martin Fuzzey [Sat, 6 Jun 2009 14:36:44 +0000 (16:36 +0200)]
MXC : update i.MX21 clock support for USB host.
* Use correct clkdev style usb clock name
* Implement rate setting for USB clock
* Introduce _clk_generic_round_rate to factorize the (now 3) uses of rounding code.
Signed-off-by: Martin Fuzzey <mfuzzey@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[ARM] 5541/1: serial/amba-pl011.c: add support for the modified port found in Nomadik
The Nomadik 8815 SoC has a slightly modified version of the PL011 block.
The patch uses the different ID value as a key to select a vendor
structure that is used to keep track of the differences, as suggested
by Russell King.
Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sascha Hauer wrote:
> On Tue, Jun 02, 2009 at 04:18:42PM -0400, Daniel Schaeffer wrote:
>> Add basic support for the Logic i.MX27LITE board.
>>
>> Signed-off-by: Daniel Schaeffer <daniel.schaeffer@timesys.com>
>
> Besides the comment made by Fabio this looks ok to me.
>
> Sascha
>
>
Fixed issues pointed out by Fabio and Magnus, and rebased to mxc-master head.
Signed-off-by: Daniel Schaeffer <daniel.schaeffer@timesys.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Daniel Mack [Sun, 31 May 2009 10:57:22 +0000 (12:57 +0200)]
Support for lilly-1131 modules and baseboards [v2]
On Thu, May 28, 2009 at 08:42:23PM +0200, Sascha Hauer wrote:
> > > Mail-Followup-To: Daniel Mack <daniel@caiaq.de>,
> > > linux-arm-kernel@lists.arm.linux.org.uk
> >
> > ... which causes my mutt to only reply to the list.
>
> Ah, ok. /me hacking in muttrc... Does it work now?
Yep :)
> > mxc_register_device(&mxc_uart_device0, &uart_pdata);
> > + mxc_register_device(&mxc_uart_device1, &uart_pdata);
> > + mxc_register_device(&mxc_uart_device2, &uart_pdata);
>
> What about the RXD3/TXD3 pins?
You're right - I got the IOMUX tables wrong and thought UART0 pins are
selected unconditionally. But as it turns out TXD1/RXD1 is for UART0
(mxc_uart_device0), TXD2/RXD2 for UART1 (mxc_uart_device1) etc.
Below is a new patch.
Thanks,
Daniel
From e7eb5fa0fed09d667a4b2f168fe466e2cc645abb Mon Sep 17 00:00:00 2001
From: Daniel Mack <daniel@caiaq.de>
Date: Wed, 27 May 2009 12:22:51 +0200
Subject: [PATCH] ARM: MX3: add two more UARTs to lilly-1131-db
Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marek Vašut [Thu, 21 May 2009 12:11:05 +0000 (13:11 +0100)]
[ARM] 5522/1: PalmLD: IDE support
Support for Palm LifeDrive's internal harddrive.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
David Brownell [Thu, 7 May 2009 16:31:42 +0000 (09:31 -0700)]
davinci: add SRAM allocator
Provide a generic SRAM allocator using genalloc, and vaguely
modeled after what AVR32 uses. This builds on top of the
static CPU mapping set up in the previous patch, and returns
DMA mappings as requested (if possible).
Compared to its OMAP cousin, there's no current support for
(currently non-existent) DaVinci power management code running
in SRAM; and this has ways to deallocate, instead of being
allocate-only.
The initial user of this should probably be the audio code,
because EDMA from DDR is subject to various dropouts on at
least DM355 and DM6446 chips.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
David Brownell [Fri, 1 May 2009 00:35:48 +0000 (17:35 -0700)]
davinci: soc-specific SRAM setup
Package on-chip SRAM. It's always accessible from the ARM, so
set up a standardized virtual address mapping into a 128 KiB
area that's reserved for platform use.
In some cases (dm6467) the physical addresses used for EDMA are
not the same as the ones used by the ARM ... so record that info
separately in the SOC data, for chips (unlike the OMAP-L137)
where SRAM may be used with EDMA.
Other blocks of SRAM, such as the ETB buffer or DSP L1/L2 RAM,
may be unused/available on some system. They are ignored here.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:42:06 +0000 (12:42 -0700)]
davinci: Move PINMUX defines to SoC files
Different SoC have different numbers of pinmux registers and other
resources that overlap with each other. To clean up the code and
eliminate defines that overlap with each other, move the PINMUX
defines to the SoC specific files.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:41:54 +0000 (12:41 -0700)]
davinci: Add compare register support to timer code
The Timer64p timer has 8 compare registers that can
be used to generate interrupts when the timer value
matches the compare reg's value. They do not disturb
the timer itself. This can be useful when there is
only one timer available for both clock events and
clocksource.
When enabled, the clocksource remains a continuous
32-bit counter but the clock event will no longer
support periodic interrupts. Instead only oneshot
timers will be supported and implemented by setting
the compare register to the current timer value plus
the period that the clock event subsystem is requesting.
Compare registers support is enabled automatically
when the following conditions are met:
1) The same timer is being used for clock events
and clocksource.
2) The timer is the bottom half (32 bits) of the
64-bit timer (hardware limitation).
3) The the compare register offset and irq are
not zero.
Since the timer is always running, there is a hardware
race in timer32_config() between reading the current
timer value, and adding the period to the current
timer value and writing the compare register.
Testing on a da830 evm board with the timer clocked
at 24 MHz and the processor clocked at 300 MHz,
showed the number of counter ticks to do this ranged
from 20-53 (~1-2.2 usecs) but usually around 41 ticks.
This includes some artifacts from collecting the
information. So, the minimum period should be
at least 5 usecs to be safe.
There is also an non-critical lower limit that
the period should be since there is no point in
setting an event that is much shorter than the
time it takes to set the event, and get & handle
the timer interrupt for that event. There can
also be all sorts of delays from activities
occuring elsewhere in the system (including
hardware activitis like cache & TLB management).
These are virtually impossible to quantify so a
minimum period of 50 usecs was chosen. That will
certianly be enough to avoid the actual hardware
race but hopefully not large enough to cause
unreasonably course-grained timers.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:41:40 +0000 (12:41 -0700)]
davinci: Integrate cp_intc support into low-level irq code
Integrate the Common Platform Interrupt Controller (cp_intc)
support into the low-level irq handling for davinci and similar
platforms. Do it such that support for cp_intc and the original
aintc can coexist in the same kernel binary.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:40:56 +0000 (12:40 -0700)]
davinci: Move emac platform_data to SoC-specific files
Since most of the emac platform_data is really SoC specific
and not board specific, move it to the SoC-specific files.
Put a pointer to the platform_data in the soc_info structure
so the board-specific code can set some of the platform_data
if it needs to.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 18 Mar 2009 17:36:08 +0000 (12:36 -0500)]
davinci: Move serial platform_device into SoC-specific files
Currently, there is one set of platform_device and platform_data
structures for all DaVinci SoCs. The differences in the data
between the various SoCs is handled by davinci_serial_init()
by checking the SoC type. However, as new SoCs appear, this
routine will become more & more cluttered.
To clean up the routine and make it easier to add support for new
SoCs, move the platform_device and platform_data structures into the
SoC-specific code and use the SoC infrastructure to provide access
to the data.
In the process, fix a bug where the wrong irq is used for uart2
of the dm646x.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:40:35 +0000 (12:40 -0700)]
davinci: Make GPIO code more generic
The current gpio code needs to know the number of
gpio irqs there are and what the bank irq number is.
To determine those values, it checks the SoC type.
It also assumes that the base address and the number
of irqs the interrupt controller uses is fixed.
To clean up the SoC checks and make it support
different base addresses and interrupt controllers,
have the SoC-specific code set those values in
the soc_info structure and have the gpio code
reference them there.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch update the common clock.c file for OMAP4. The clk_get() and
clk_put() functions are moved to common place in arch/arm/common/clkdev.c
Since on current OMAP4 platform clk management is still not supported, the
platform file is stubbed with those functions.
Once the framework is ready, this WILL be replaced with a full
clkdev implementation.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.
OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
David Brownell [Thu, 28 May 2009 21:04:03 +0000 (14:04 -0700)]
ARM: OMAP3: mmc-twl4030 uses regulator framework
Decouple the HSMMC glue from the twl4030 as the only
regulator provider, using the regulator framework instead.
This makes the glue's "mmc-twl4030" name become a complete
misnomer ... this code could probably all migrate into the
HSMMC driver now.
Tested on 3430SDP (SD and low-voltage MMC) and Beagle (SD),
plus some other boards (including Overo) after they were
converted to set up MMC regulators properly.
Eventually all boards should just associate a regulator with
each MMC controller they use. In some cases (Overo MMC2 and
Pandora MMC3, at least) that would be a fixed-voltage regulator
with no real software control. As a temporary hack (pending
regulator-next updates to make the "fixed.c" regulator become
usable) there's a new ocr_mask field for those boards.
Patch updated with a fix for disabling vcc_aux by
Adrian Hunter <adrian.hunter@nokia.com>
Cc: Pierre Ossman <drzeus-list@drzeus.cx> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
Paul Walmsley [Thu, 28 May 2009 21:03:59 +0000 (14:03 -0700)]
ARM: OMAP3: SDRC: add timing data for Micron MT46H32M32LF-6, v2
Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the
OMAP3 Beagle and EVM boards. Original timing data is from the Micron
datasheet PDF downloaded from:
Make 770 LCD work by adding clk_add_alias().
Also remove the old unused functions.
Note that the clk_add_alias() could probably be moved
to arch/arm/clkdev.c later on.
Cc: linux-fbdev-devel@lists.sourceforge.net Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com
Tony Lindgren [Thu, 28 May 2009 20:23:52 +0000 (13:23 -0700)]
ARM: OMAP2/3: Add generic smc91x support when connected to GPMC
Convert the board-rx51 smc91x code to be generic and make
the boards to use it. This allows future recalculation of the
timings when the source clock gets scaled.
Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL.
Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing
calculations.
Juha Yrjola [Thu, 28 May 2009 20:23:52 +0000 (13:23 -0700)]
ARM: OMAP2/3: Add generic onenand support when connected to GPMC
Add generic onenand support when connected to GPMC and make the
boards to use it.
The patch has been modified to make it more generic to support all
the boards with GPMC. The patch also remove unused prototype for
omap2_onenand_rephase(void).
Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC
and setting the GPMC timings in the bootloader. Setting the GPMC
timings in the bootloader will not allow supporting frequency
scaling for the onenand source clock.
Original OMAP DMA chaining design had chain_id as one of the callback
parameters. Patch 538528de0cb256f65716ab2e9613d9e920f97fe2 changed it
to use logical channel instead.
Correct the naming for callback to also use logical channel number
instead of the chain_id.
Kevin Hilman [Tue, 28 Apr 2009 22:27:44 +0000 (15:27 -0700)]
OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.
Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Jouni Hogander [Tue, 9 Dec 2008 11:36:50 +0000 (13:36 +0200)]
OMAP: UART: Add sysfs interface for adjusting UART sleep timeout
This patch makes it possible to change uart sleep timeout. New sysfs
entry is added (/sys/devices/platform/serial8250.<uart>/sleep_timeout)
Writing zero will disable the timeout feature and prevent UART clocks
from being disabled.
Also default timeout is increased to 5 second to make serial console
more usable.
Original patch was written by Tero Kristo.
Cc: Tero Kristo <Tero.Kristo@nokia.com> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Kevin Hilman [Wed, 4 Feb 2009 18:51:40 +0000 (10:51 -0800)]
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Kevin Hilman [Thu, 28 May 2009 17:56:16 +0000 (10:56 -0700)]
OMAP2/3: PM: push core PM code from linux-omap
This patch is to sync the core linux-omap PM code with mainline. This
code has evolved and been used for a while the linux-omap tree, but
the attempt here is to finally get this into mainline.
Following this will be a series of patches from the 'PM branch' of the
linux-omap tree to add full PM hardware support from the linux-omap
tree.
Much of this PM core code was written by Jouni Hogander with
significant contributions from Paul Walmsley as well as many others
from Nokia, Texas Instruments and linux-omap community.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
changes since v1: we now check if the parent configuration bit was
changed since reset and change the parent when needed.
csi_clk parent was defined with ahb_clk. However, according to the
m31 reference manual, it should be serial_pll_clk.
Guennadi always used a 20 MHz clock that was by chance changed to
a 45 MHz that fits in the mt9t031 spec. Now the clocks are computed
and output correctly (measured on oscillo).
Catalin Marinas [Mon, 18 May 2009 15:26:27 +0000 (16:26 +0100)]
[ARM] 5516/1: Flush the D-cache after initialising the SCU
On MP systems, the data loaded by CPU0 before the SCU was initialised
may not be visible to the other CPUs.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This also includes the following compile fix:
This patch includes 'asm/cacheflush.h' which is needed to use
'flush_cache_all()' function.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adding a disable hook to the irq_chip is not the way to fix the
problem being addressed by this patch. Instead, we need to fix
support for [enable|disable]_irq_wake().
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:40:21 +0000 (12:40 -0700)]
davinci: Add watchdog base address flexibility
The watchdog code currently hardcodes the base address
of the timer its using. To support new SoCs, make it
support timers at any address. Use the soc_info structure
to do this.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:40:11 +0000 (12:40 -0700)]
davinci: Add base address and timer flexibility
The davinci timer code currently hardcodes the timer register
base addresses, the timer irq numbers, and the timers to use
for clock events and clocksource. This won't work for some
a new SoC so put those values into the soc_info structure
and set them up in the SoC-specific files.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:40:00 +0000 (12:40 -0700)]
davinci: Move interrupt ctlr info to SoC infrastructure
Use the SoC infrastructure to hold the interrupt controller
information (i.e., base address, default priorities,
interrupt controller type, and the number of IRQs).
The interrupt controller base, although initially put
in the soc_info structure's intc_base field, is eventually
put in the global 'davinci_intc_base' so the low-level
interrupt code can access it without a dereference.
These changes enable the SoC default irq priorities to be
put in the SoC-specific files, and the interrupt controller
to be at any base address.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:39:48 +0000 (12:39 -0700)]
davinci: Move pinmux setup info to SoC infrastructure
The pinmux register base and setup can be different for different
SoCs so move the pinmux reg base, pinmux table (and its size) to
the SoC infrastructure.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:39:33 +0000 (12:39 -0700)]
davinci: Add support for multiple PSCs
The current code to support the DaVinci Power and Sleep Controller (PSC)
assumes that there is only one controller. This assumption is no longer
valid so expand the support to allow greater than one PSC.
To accomplish this, put the base addresses for the PSCs in the SoC
infrastructure so it can be referenced by the PSC code. This also
requires adding an extra parameter to davinci_psc_config() to specify
the PSC that is to be enabled/disabled.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:39:09 +0000 (12:39 -0700)]
davinci: Support JTAG ID register at any address
The Davinci cpu_is_davinci_*() macros use the SoC part number
and variant retrieved from the JTAG ID register to determine the
type of cpu that the kernel is running on. Currently, the code to
read the JTAG ID register assumes that the register is always at
the same base address. This isn't true on some newer SoCs.
To solve this, have the SoC-specific code set the JTAG ID register
base address in soc_info structure and add a 'cpu_id' member to it.
'cpu_id' will be used by the cpu_is_davinci_*() macros to match
the cpu id. Also move the info used to identify the cpu type into
the SoC-specific code to keep all SoC-specific code together.
The common code will read the JTAG ID register, search through
an array of davinci_id structures to identify the cpu type.
Once identified, it will set the 'cpu_id' member of the soc_info
structure to the proper value and the cpu_is_davinci_*() macros
will now work.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 15 Apr 2009 19:38:58 +0000 (12:38 -0700)]
davinci: Encapsulate SoC-specific data in a structure
Create a structure to encapsulate SoC-specific information.
This will assist in generalizing code so it can be used by
different SoCs that have similar hardware but with minor
differences such as having a different base address.
The idea is that the code for each SoC fills out a structure
with the correct information. The board-specific code then
calls the SoC init routine which in turn will call a common
init routine that makes a copy of the structure, maps in I/O
regions, etc.
After initialization, code can get a pointer to the structure
by calling davinci_get_soc_info(). Eventually, the common
init routine will make a copy of all of the data pointed to
by the structure so the original data can be made __init_data.
That way the data for SoC's that aren't being used won't consume
memory for the entire life of the kernel.
The structure will be extended in subsequent patches but
initially, it holds the map_desc structure for any I/O
regions the SoC/board wants statically mapped.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Kevin Hilman [Wed, 29 Apr 2009 19:10:55 +0000 (12:10 -0700)]
davinci: DM355: add base SoC and board support
In addition, add board support for the DM355 Evaluation Module (EVM)
and the DM355 Leopard board.
Original DM355 EVM support done by Sandeep Paulraj, with significant
updates and improvements by David Brownell. DM355 Leopord support
done by Koen Kooi.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Koen Kooi <koen@beagleboard.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Sergei Shtylyov [Wed, 11 Mar 2009 15:49:05 +0000 (19:49 +0400)]
davinci: INTC: add support for TI cp_intc
Add support for Texas Instuments Common Platform Interrupt Controller
(cp_intc) used on DA830/OMAP-L137.
Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mark Greer <mgreer@mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Mark A. Greer [Wed, 18 Feb 2009 21:00:36 +0000 (14:00 -0700)]
davinci: support different UART bases for zImage uncompress
The davinci pre-kernel boot code assumes that all platforms use the
same UART base address for the console. That assumption is not longer
valid with some newer SoCs so determine the console UART base address
from the machine number passed in from bootloader.
Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch attempts to solve the low-level debug issue in DM646x. The
UART on DM646x SoC allows only 32-bit access. The existing
debug-macro.S uses the macros from debug-8250.S file. This led to
garbage serial out in the case of DM646x.
The inclusion of debug-8250.S does not allow for run time fix for this
issue. There are compile time errors due to multiple definitions of
the macros. Also when building a single image for multiple DaVinci
Platforms, the ifdefs cannot be relied upon.
The solution below does not include the debug-8250.S file and defines
the necessary macros. This solution was arrived at after observing
that word access does not affect the low-level debug messages on
DM644x/DM355.
The other approach to this issue is to use the UART module information
available in the peripheral registers to decide the access
mechanism. But this will have to be done for every access of UART
specifically for DM646x. Also this calls for a modification of the
debug-8250.S file.
Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
David Brownell [Mon, 4 May 2009 20:14:27 +0000 (13:14 -0700)]
davinci: gpio irq enable tweaks
Fix two IRQ triggering bugs affecting GPIO IRQs:
- Make sure enabling with IRQ_TYPE_NONE ("default, unspecified")
isn't a NOP ... default to both edges, at least one must work.
- As noted by Kevin Hilman, setting the irq trigger type for a
banked gpio interrupt shouldn't enable irqs that are disabled.
Since GPIO IRQs haven't been used much yet, it's not clear these
bugs could have affected anything. The few current users don't
seem to have been obviously suffering from these issues.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Alberto Panizzo [Mon, 25 May 2009 20:35:38 +0000 (22:35 +0200)]
ARM MXC: Atmark Armadillo 500 board support.
On Mon, 25 May 2009 18:33:28 +0200
Valentin Longchamp <valentin.longchamp@epfl.ch> wrote:
> Hello,
>
> I have updated my mxc git tree and given a compilation spin to your
> board support and I have comments. See below.
>
>
> What's the point of declaring this new function, if all it does is
> calling the already existing one ? Furthermore, in the current
> mxc-master tree, mxc_map_io() does not exist anymore, it should be
> mx31_map_io (this breaks compilation for your board).
>
This patch solve those two issues. Until now i based my patches to
vanilla tree. This evening I cloned the mxc-master tree so i could
update the armadillo 500 support within recent platform changes.
The patch:
From e986a8dc262e5292350d95bf65ead75baf3272d7 Mon Sep 17 00:00:00 2001
From: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Date: Mon, 25 May 2009 22:24:03 +0200
Subject: [PATCH] Armadillo 500 removing useless function armadillo5x0_map_io
and use machine specific io mapping
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
projects / linux-beck.git / log