Michael Minnick [Tue, 9 Oct 2012 23:06:31 +0000 (18:06 -0500)]
ENGR00229290 EPDC: MX6: Adjust number of LUTs for 5-bit waveform
When a 5-bit waveform is loaded, the maximum number of available
LUTs is 16. The LUT allocator must account for this.
Note that 5-bit waveform loading is currently not supported in the
driver. However, this fix makes sure the LUT allocator is correct
when 5-bit support is added.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Ryan QIAN [Mon, 8 Oct 2012 23:44:34 +0000 (07:44 +0800)]
ENGR00227420 mmc: sdhci: shorten the delay on disabling clk
- change the delay from 10 * HZ to 1 * HZ, though (1 * HZ) might not be the
best, just as a base.
1. Since the request has been moved out of interrupt context, there will be no
more calling enable_clk in interrupt context. So it's not necessary to keep
such a long delay on disabling clock in order to save power.
2. Still keeping the 1*HZ of delay is to avoid frequently enabling/disabling
clock.
make shi [Fri, 12 Oct 2012 09:01:33 +0000 (17:01 +0800)]
ENGR00229354 Mx6 USB device: fix wrong handle for invalid USB_FEATURE requests
There is a bug udc driver handle invalid USB_FEATURE requests in current bsp.
The invalid USB_FEATURE request will be handled as a valid USB_FEATURE request.
We should set protocol stall on ep0 to handle invalid USB_FEATURE requests.
Terry Lv [Fri, 12 Oct 2012 06:39:34 +0000 (14:39 +0800)]
ENGR00229327: otp: driver causes warning when enable CONFIG_LOCKDEP
When CONFIG_LOCKDEP is enabled, it will cause warings:
------------[ cut here ]------------
WARNING: at kernel/lockdep.c:2885 sysfs_add_file_mode+0x54/0xc0()
Modules linked in:
[<80046364>] (unwind_backtrace+0x0/0xfc) from [<800758c0>]
(warn_slowpath_common+0x4c/0x64)
[<800758c0>] (warn_slowpath_common+0x4c/0x64) from [<800758f4>]
(warn_slowpath_null+0x1c/0x24)
[<800758f4>] (warn_slowpath_null+0x1c/0x24) from [<801536c4>]
(sysfs_add_file_mode+0x54/0xc0)
[<801536c4>] (sysfs_add_file_mode+0x54/0xc0) from [<8015616c>]
(internal_create_group+0xdc/0x1d8)
[<8015616c>] (internal_create_group+0xdc/0x1d8) from [<80524110>]
(fsl_otp_probe+0x168/0x1d4)
[<80524110>] (fsl_otp_probe+0x168/0x1d4) from [<802b42e8>]
(platform_drv_probe+0x18/0x1c)
[<802b42e8>] (platform_drv_probe+0x18/0x1c) from [<802b2fe4>]
(driver_probe_device+0x98/0x1a4)
[<802b2fe4>] (driver_probe_device+0x98/0x1a4) from [<802b3184>]
(__driver_attach+0x94/0x98)
[<802b3184>] (__driver_attach+0x94/0x98) from [<802b280c>]
(bus_for_each_dev+0x60/0x8c)
[<802b280c>] (bus_for_each_dev+0x60/0x8c) from [<802b2180>]
(bus_add_driver+0x190/0x268)
[<802b2180>] (bus_add_driver+0x190/0x268) from [<802b3788>]
(driver_register+0x78/0x13c)
[<802b3788>] (driver_register+0x78/0x13c) from [<800394ac>]
(do_one_initcall+0x30/0x170)
[<800394ac>] (do_one_initcall+0x30/0x170) from [<800083cc>]
(kernel_init+0x98/0x144)
[<800083cc>] (kernel_init+0x98/0x144) from [<8004003c>]
(kernel_thread_exit+0x0/0x8)
---[ end trace 877415a10b5d9cb1 ]---
also, on imx6sl, it will cause below issue:
BUG: key bffea2e4 not in .data!
BUG: key bffea300 not in .data!
BUG: key bffea31c not in .data!
BUG: key bffea338 not in .data!
BUG: key bffea354 not in .data!
BUG: key bffea370 not in .data!
BUG: key bffea38c not in .data!
BUG: key bffea3a8 not in .data!
BUG: key bffea3c4 not in .data!
BUG: key bffea3e0 not in .data!
BUG: key bffea3fc not in .data!
BUG: key bffea418 not in .data!
BUG: key bffea434 not in .data!
BUG: key bffea450 not in .data!
BUG: key bffea46c not in .data!
BUG: key bffea488 not in .data!
BUG: key bffea4a4 not in .data!
BUG: key bffea4c0 not in .data!
BUG: key bffea4dc not in .data!
We need to call sysfs_attr_init to initlize sysfs attr.
Huang Shijie [Thu, 11 Oct 2012 01:50:13 +0000 (09:50 +0800)]
ENGR00227835 imx6q: gpmi: fix the warning when no NAND chip exits
If there is no nand chip in the board, the kernel will prints out the
following warning message:
------------[ cut here ]------------
WARNING: at arch/arm/plat-mxc/clock.c:63 clk_disable+0x48/0x90()
clock enable/disable mismatch! clk apbh_dma_clk
Modules linked in:
[<80044f48>] (unwind_backtrace+0x0/0xfc) from
[<80070ac0>] (warn_slowpath_common+0x4c/0x64)
[<80070ac0>] (warn_slowpath_common+0x4c/0x64) from
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40)
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40) from
[<8005ee60>] (clk_disable+0x48/0x90)
[<8005ee60>] (clk_disable+0x48/0x90) from
[<80255e48>] (dma_chan_put+0x4c/0x50)
[<80255e48>] (dma_chan_put+0x4c/0x50) from
[<80255f18>] (dma_release_channel+0x24/0x94)
[<80255f18>] (dma_release_channel+0x24/0x94) from
[<802ad8ec>] (release_resources+0x58/0x6c)
[<802ad8ec>] (release_resources+0x58/0x6c) from
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec)
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec) from
[<80281868>] (platform_drv_probe+0x18/0x1c)
[<80281868>] (platform_drv_probe+0x18/0x1c) from
[<80280590>] (driver_probe_device+0x98/0x1a4)
[<80280590>] (driver_probe_device+0x98/0x1a4) from
[<80280728>] (__driver_attach+0x8c/0x90)
[<80280728>] (__driver_attach+0x8c/0x90) from
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c)
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c) from
[<8027f75c>] (bus_add_driver+0x184/0x25c)
[<8027f75c>] (bus_add_driver+0x184/0x25c) from
[<80280d1c>] (driver_register+0x78/0x13c)
[<80280d1c>] (driver_register+0x78/0x13c) from
[<80022d80>] (gpmi_nand_init+0xc/0x3c)
[<80022d80>] (gpmi_nand_init+0xc/0x3c) from
[<80039478>] (do_one_initcall+0x30/0x16c)
[<80039478>] (do_one_initcall+0x30/0x16c) from
[<80008410>] (kernel_init+0x98/0x144)
[<80008410>] (kernel_init+0x98/0x144) from
[<8003ffb4>] (kernel_thread_exit+0x0/0x8)
---[ end trace c28d32057fe33a29 ]---
This mxs_dma_clk's usecount is not correctly changed which causes the kernel
shows this warning.
This patch adds proper clk_disable_unprepare/clk_prepare_enable in
the mxs-dma driver to balance the mxs_dma_clk's usecount.
Also put the mxs_dma_clk when the gpmi exits.
Liu Ying [Wed, 10 Oct 2012 07:13:30 +0000 (15:13 +0800)]
ENGR00227681 IPUv3:Use spinlock to protect buf ready reg
There are several channels' buffer ready bits controlled
by a single 32bit register-IPU_CHA_BUFx_RDY. These buffer
ready can be write-one-to-set or write-one-to-clear, which
is controlled by IPU_GPR register. v4l2 capture driver will
touch the buffer ready registers in interrupt context, so,
currently, ipu->mutex_lock is bypassed with the context.
Then, a race condition is that v4l2 capture driver interrupt
context tries to set a channel buffer ready, while, another
context tries to disable another channel(clear buffer ready
bit), which may cause v4l2 capture driver fails to set buffer
ready(SMFC0_FRM_LOST error may happen). This patch uses ipu->
rdy_reg_spin_lock to protect buffer ready registers to fix
the race condition issue and rename ipu->spin_lock to ipu->
int_reg_spin_lock.
1) We get busy_lock semaphore before we get a dqueue event, so, when user
is blocked at DQBUF ioctrl, the user will also be blocked at QBUF ioctrl,
then the video performance will drop. This patch changes to get busy_lock
semaphore to protect DQBUF ioctrl until we successfully get a dqueue event.
2) Use queue_int_lock and dqueue_int_lock spinlocks to protect working_q/
ready_q/done_q in the end of frame interrupt handler camera_callback(), in
case, the handler and VIDIOC_QBUF/VIDIOC_DQBUF ioctrls are called on diff-
erent cores at the same time.
3) Protect ready_q with queue_int_lock spinlock in mxc_streamon(), in case,
VIDIOC_STREAMON and VIDIOC_QBUF ioctrls are called on different cores at
the same time.
1) Change to enable/disable mclk only in open, release,
suspend and resume functions, since we may simply think that
sensor or mclk will be used soon after cam->open_count is non-zero.
2) Fix a bug when calling ipu_csi_enable_mclk_if() with wrong
parameter(cam->csi should be cam->mclk_source) in mxc_v4l2_close()
and in mxc_v4l2_s_ctrl() with V4L2_CID_MXC_SWITCH_CAM control id.
Robby Cai [Tue, 9 Oct 2012 11:59:25 +0000 (19:59 +0800)]
ENGR00227568 elcdif: fix fb wait for vsync timeout when suspend and resume
When suspend, the lcdif and panel will be stopped. When resume, fb_set_par()
will be called, in which the lcdif and the panel will be re-initialized.
However, fb_set_par() also checks the parameters via mxc_elcdif_fb_par_equal(),
which will probably make fb_set_par() just return with them un-initialized.
And thus, the interrupt will not come. This patch added a varible to check
whether they're running along with mxc_elcdif_fb_par_equal() checking to
fix the issue. If not running, re-initialization will be forcely done.
Robby Cai [Tue, 9 Oct 2012 08:36:41 +0000 (16:36 +0800)]
ENGR00227502-1 csi/v4l2: Implement probe and remove function for csi v4l2 driver
Because csi_v4l2 driver will only be loaded when needed(by assign 'csi' in
kernel cmdline), we use standard driver framework to easily bind the device and
driver. Otherwise, we will meet the problem like the crash as below when do
suspend/resume due to the resource of csi not assigned at all if 'csi' not
passed in cmdline.
Anson Huang [Tue, 9 Oct 2012 19:30:20 +0000 (15:30 -0400)]
ENGR00227477 mx6qdl: system resume fail due to DDR not accessable
For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Ryan QIAN [Mon, 8 Oct 2012 01:50:23 +0000 (09:50 +0800)]
ENGR00227241 mx6sl: clk: sdhc can not work at lp idle mode
issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
Ryan QIAN [Tue, 9 Oct 2012 00:58:41 +0000 (08:58 +0800)]
ENGR00220469 mmc: sdio: claim host on suspend and release on resuming
issue:
Since there's no sync mechanism between sdio bus suspending and sdio_irq_thread,
it will cause that sdio_irq_thread still makes sdhc request even after sdio bus
suspends.
fix:
On suspending sdio bus, claim host, so that:
1. mmc_sdio_suspend will wait for finishing of sdio_irq_thread.
2. sdio_irq_thread will be blocked even being scheduled.
And release host on resuming.
Acked-by: Aisheng DONG <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
Currently, the sequence and functionality we use to enter and exit
suspend causes us to hang upon resuming. It appears that this is being
caused by two things. The first is the powering off of the 2p5 rail
which powers the IO pullups and pulldowns. The DQS pins were
configured as pull downs. The second is switching the DQS pins from
differential to CMOS mode (and back). This second problem only
occurs on a few EVK boards.
It is believed that these changes are causing glitches on the mmdc DQS
pins which is putting garbage in the FIFO (or causing some other FIFO
problem). This patch adds two mmdc0 FIFO resets after exiting the
suspend. Two are thought to be needed per previous FIFO reset
experience by Mike Kjar.
Since the MMDC0 FIFO will be cleaned each time, we can now remove
the code that configured the DQS lines as pull downs as we no
longer care if they float.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
Robert Lee [Mon, 8 Oct 2012 21:15:27 +0000 (16:15 -0500)]
ENGR00227422: ARM: imx6sl: Adjust ARM and SOC stby voltages
According to the latest specification data, these rails should
go no lower than 900mV in standby mode. This patch modifies
the existing mx6sl board files and sets the pmic standby voltage
for these rails to be 925mV (extra 25mV to account for pmic accuracy).
Signed-off-by: Robert Lee <robert.lee@freescale.com>
ENGR00227426 MX6SL-Fix bugs in low power IDLE mode
Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Anson Huang [Tue, 9 Oct 2012 15:04:42 +0000 (11:04 -0400)]
ENGR00227425 mx6sl: Need to save all registers before calling C function
Different linker may use r12, we should save/restore all
registers(r0-r12) before calling C function to prevent
these registers from corruption in C code.
ENGR00227245 mx6q: Remove 400M setpoint for bus freq
Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
ENGR00227249 MX6SL-Add support for low latency STANDBY mode.
Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
* Fix imx_dma_data duplicate struct definition
* Rename struct as name conflicts with imx_dma_data
struct defined at arch/arm/plat-mxc/include/mach/dma.h
* Update copyrigth year.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Michael Minnick [Wed, 26 Sep 2012 21:33:21 +0000 (16:33 -0500)]
ENGR00180348 EPDC: invalid data when width is 2048 or greater
This patch works around the 6DLS and 6SL chip errata:
ERR005313 EPDC: Incorrect data fetched when the buffer update width is
2048 pixels or greater
This patch breaks large updates into multiple updates, which works
around the problem on both 6DSL and 6SL. This patch does not use the
Group Update feature, which may improve things further on 6SL.
This patch does not include for support for any particular large panel.
It was tested on ED09705 (2400x1650). Support for ED09705 is
available in a separate patch.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Robby Cai [Thu, 27 Sep 2012 15:50:08 +0000 (23:50 +0800)]
ENGR00225981-8 csi/imx6sl: add the platform-related setting
- add platform data for csi driver
- change the regulator name to reflect the voltage really used
- select OSC as csi parent clock to get 24MHz
- add an boot option to use csi feature while filter out the EPDC/SPDC, since
there are pin conflicts with xPDC.
- both ov5640 and ov5642 are verified okay, ov5640 is used by default.
- remove IPU from update_defconfig
ENGR00225960-02 FB: Support sii902x HDMI driver in ELCDIF FB
- Added mxcfb_elcdif_register_mode function.
- Create video mode list, and check default video mode
with video mode list before setting.
- Adjust elcdif pixel clock setting, reconfig elcdif pixel
parent clock video pll, get more accurate pixel clock
according video mode.
- Added video mode dump function for debug
Robin Gong [Tue, 25 Sep 2012 08:47:48 +0000 (16:47 +0800)]
ENGR00225735-3 GPU: add gpu regulator disable/enable in gpu driver
add gpu regulator management in gpu driver Signed-off-by: Robin Gong <b38343@freescale.com> Acked-by: Lily Zhang Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Tue, 25 Sep 2012 08:43:57 +0000 (16:43 +0800)]
ENGR00225735-2 VPU: add vpu regulator enable/disable in driver
add vpu regulator management including enable/disable in vpu driver. Mainly
in open/release and suspend/resume. Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Tue, 25 Sep 2012 08:33:37 +0000 (16:33 +0800)]
ENGR00225735-1 PU anatop: PU regulator can be disabled/enabled by drivers
Before, PU regulator only be turned off in DSM, which means it kept on in
system normal mode even GPU/VPU driver didn't run. To decrease power number,
PU regulator can be disabled/enabled by GPU/VPU driver, and the voltage value
is tracked by VDDARM which change in cpufreq driver.The patch including:
1.implement PU regulator enable/disable interface in anatop regulator driver
2.remove gpu_power_down and gpu_power_up in system suspend/resume flow.
3.skip change pu regulator set if it has been disabled.
Note: There is three power supply on VDDPU:
a).Use internal anatop PU regulator, VDDDPU_IN is fixed. In this case,VDDPU_CAP
can be turned off or dynamic change by internal anatop(track with VDDSOCi_CAP).
In other words, it use "cpu_vddvpu" regulator as PU regulator,not only in GPU/
VPU driver, but also in cpufreq driver.Sabresd,Sololite EVK is in this case if
disable CONFIG_MX6_INTER_LDO_BYPASS.
b).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS).But VDDPU_IN is connected with VDDSOC_IN. Because
VDDSOC can't be turned off for ever, and VDDPU track with VDDSOC always, we
remove "pu_id", so that cpufreq driver will never touch it.But GPU/VPU driver
will turn off/on VDDPU_CAP by disabling/enabling "cpu_vddvpu".In this case,
although VDDPU_IN is supplied by external pmic in hardware level, but we can't
turn off external pmic directly, because it connect with VDDSOC_IN.So only we
can do is turn off VDDPU_CAP by internal anatop regulator("cpu_vddvpu").Sabresd
,Sololite EVK is in this case if enable CONFIG_MX6_INTER_LDO_BYPASS.
c).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS). And VDDPU_IN is in dependent with VDDSOC_IN(
whether short in VDDPU_IN with VDDPU_CAP directly or not).In this case,the only
thing we need to do is that add the right external vddpu regulator name to
"pu_id" in their boad file, and nothing else.
Just like below (arch/arm/mach-mx6/board-mx6sl_evk.c):
static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
*******************************************************************
.pu_id = "what you used VDDPU_IN regulator name from external pmic"
*******************************************************************
.reg_id = "cpu_vddgp",
.soc_id = "cpu_vddsoc",
.pu_id = "cpu_vddvpu",
......
ENGR00225894 MX6SL-Improve system IDLE power numbers
Add the following power optimizations when all PLLs
are either disabled or in bypass:
1. Disable 2P5 in system IDLE mode and enable weak 2P5.
2. Set OSC bias current to -37.5% just before the WFI instruction
and set it back to 0% after WFI.
3. Enable the low power bandgap and power down the regular
bandgap.
ENGR00226080 Update GC2000/GC320 AXI bus cache attribute
This patch changed the GPU AXI bus cache attribute
to improve the performance of fillrate bound case.
Here is some test result: BEFORE:AFTER (larger better)
mm06 samruai fps: 117.74:137.64
mm06 proxycon fps: 117.90:135.00
Fillrate with 1 tex: 251.3M:331.1M
Fillrate with 2 tex: 402.6M:475.4M
Ryan QIAN [Thu, 27 Sep 2012 08:12:56 +0000 (16:12 +0800)]
ENGR00226096 mx6sl: remove high set point for usdhc
- Due to usdhc ADMA mode has issue working with low bus freq, in
driver usdhc has been configured to SDMA mode already. So it is
not necessary to keep high set point flag any more.
Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Dong Aisheng <b29396@freescale.com> Acked-by: Robby CAI <r63905@freescale.com>
This patch adds CONFIG_MX6_CLK_FOR_BOOTUI_TRANS support. Setting
this Kconfig may keep enable IPU related clocks and PWM clocks
and avoid setting IPU related clocks' parents when initializing
clock tree so that bootloader splashimage can transition to
kernel smoothly.
As there is only one IPU embedded in MX6DL and two IPUs embedded
in MX6DQ. The max ipuv3 fb platform driver number is two for
MX6DL and four for MX6DQ.
Liu Ying [Wed, 12 Sep 2012 01:43:12 +0000 (09:43 +0800)]
ENGR00223797-6 MX6 SabreSD:Initialize late init for IPUv3 fb pdata
This patch initializes late init field to false for IPUv3 fb pdata,
so we don't support late init by default unless we change them to
true in other places specificly.
Liu Ying [Wed, 12 Sep 2012 01:36:12 +0000 (09:36 +0800)]
ENGR00223797-5 MX6 SabreSD:Initialize bypass reset for IPUv3 pdata
This patch initializes bypass reset field to false for IPUv3 pdata,
so we don't support bypass reset by default unless we change them
to true in other places specificly.
Liu Ying [Tue, 11 Sep 2012 10:10:11 +0000 (18:10 +0800)]
ENGR00223797-4 IPUv3 fb:Support framebuffer late init
This patch adds late init support in IPUv3 fb driver
to avoid IPUv3 fb being re-initialized during probe if
a platform supports smooth transition from bootloader
splashimage to system UI. The re-initialization will
be delayed to the first time the user triggers
mxcfb_set_par() and unblank the framebuffer.
The following items are done to support this:
1) Move global alpha and color key setting in probe
after framebuffer is registered(before registering
we enable IPU hsp clock), because the 2 APIs enable
and disable IPU hsp clock which may cause IPU stops
running in ipuv3 fb probe function.
2) Do not clear framebuffer content in probe function
if late init is set. This is to avoid bootloader
splashimage content is cleared.
3) If late init is set, do not re-initialize and
unblank framebuffer in probe function, but initialize
and enable ipu display channel instead to enable
the ipu hsp clock. Refer to the code comment for
detail.
4) Delay register IPU interrupts used by framebuffer
until IPU hsp clock is enabled by 3). As the APIs
to register IPU interrupts may enable and disable
IPU hsp clock as well.
Liu Ying [Tue, 11 Sep 2012 10:20:39 +0000 (18:20 +0800)]
ENGR00223797-3 ARM:IPUv3 fb:Add late init in pdata
This patch adds late init field support in ipuv3 fb
platform data, so that a platform may choose to not
to initialize framebuffer until the user triggers
set_par(), which may support smooth transition from
bootloader splashimage to system UI.
Liu Ying [Tue, 11 Sep 2012 10:18:39 +0000 (18:18 +0800)]
ENGR00223797-2 IPUv3:Support bypass reset for probe
This patch adds bypass reset support in IPUv3 driver
probe function to avoid IPUv3 being reset if a plat-
form supports smooth transition from bootloader
splashimage to system UI.
Liu Ying [Tue, 11 Sep 2012 10:16:12 +0000 (18:16 +0800)]
ENGR00223797-1 ARM:IPUv3:Add bypass reset in pdata
This patch adds bypass reset field support in ipuv3
platform data, so that a platform may choose not to
reset ipuv3 when doing probe, which may support
smooth transition from bootloader splashimage to
system UI.
Wayne Zou [Thu, 30 Aug 2012 09:20:06 +0000 (17:20 +0800)]
ENGR00220747 V4L2 out: Fix mosaic and flash issue if use VDOA input crop mode
Fix bug:
A lot of mosaic and flash issue if use VDOA mode when doing video playback
on stream H264_BP13_fc_320x136_29.97_444_AAC_48_130_2_vbr.mp4.
For this special stream, the frame size is 320x144 and the stream includes
input cropping information:320x136. It needs to use 320x144 frame size to
do tiled format conversion instead of 320x128 after alignment.
Arve Hjønnevåg [Thu, 24 Feb 2011 00:51:58 +0000 (16:51 -0800)]
ARM: etm: Power down etm(s) when tracing is not enabled
Without this change a saw an 18% increase in idle power consumption
on one deivce when trace support is compiled into the kernel. Now
I see the same increase only when tracing.
Arve Hjønnevåg [Sat, 5 Feb 2011 06:38:14 +0000 (22:38 -0800)]
ARM: etm: Support multiple ETMs/PTMs.
If more than one ETM or PTM are present, configure all of them
and enable the formatter in the ETB. This allows tracing on dual
core systems (e.g. omap4).
Arve Hjønnevåg [Sat, 5 Feb 2011 06:38:14 +0000 (22:38 -0800)]
ARM: etm: Return the entire trace buffer if it is empty after reset
On some SOCs the read and write pointer are reset when the chip
resets, but the trace buffer content is preserved. If the status
bits indicates that the buffer is empty and we have never started
tracing, assume the buffer is full instead. This can be useful
if the system rebooted from a watchdog reset.
Arve Hjønnevåg [Tue, 1 Feb 2011 02:33:55 +0000 (18:33 -0800)]
ARM: etm: Configure data tracing
The old code enabled data tracing, but did not configure the
range. We now configure it to trace all data addresses by default,
and add a trace_data_range attribute to change the range or disable
data tracing.
Arve Hjønnevåg [Sat, 29 Jan 2011 07:44:43 +0000 (23:44 -0800)]
ARM: etm: Allow range selection
Trace kernel text segment by default as before, allow tracing of other
ranges by writing a range to /sys/devices/etm/trace_range, or to trace
everything by writing 0 0.
Arve Hjønnevåg [Tue, 1 Feb 2011 05:34:47 +0000 (21:34 -0800)]
ARM: etm: Don't try to clear the buffer full status after reading the buffer
If the write address was at the end of the buffer, toggling the trace
capture bit would set the RAM-full status instead of clearing it, and
if any of the stop bits in the formatter is set toggling the trace
capture bit may not do anything.
Instead use the read position to find out if the data has already
been returned.
This also fixes the read function so it works when the trace buffer is
larger than the buffer passed in from user space. The old version
would reset the trace buffer pointers after every read, so the second
call to read would always return 0.
make shi [Thu, 20 Sep 2012 09:20:14 +0000 (17:20 +0800)]
ENGR00225131-06 MX6 PM: clear stop_mode_config after system resume
- If stop_mode_config is set as 1, the USB otg vbus wakeup system can be
supported
- After system resume, need clear stop_mode_config bit to keep the 1P1
default off
make shi [Thu, 20 Sep 2012 09:15:26 +0000 (17:15 +0800)]
ENGR00225131-05 MX6 USB: set stop_mode_config bit if wake up is enabled
IC designer had clarified that 1P1 can be turned off if we do not need support
remote wakeup. So If there is no requirement for USB remote wake up, the 1P1
can be turn off. USB driver will support dynamically turn on(off) 1P1 during
system suspend. 1P1 will be turn on depend on USB wakeup is enabled.
- Set stop_mode_config bit if USB host need support USB remote wake up
- Set stop_mode_config bit if USB device need support USB DP/DM wake
up system
make shi [Thu, 20 Sep 2012 09:12:47 +0000 (17:12 +0800)]
ENGR00225131-04 MX6 USB: implement platform_phy_power_on for USB otg and h1
IC designer had clarified that 1P1 can be turned off if we do not need support
remote wakeup. So If there is no requirement for USB remote wake up, the 1P1
can be turn off. USB driver will support dynamically turn on(off) 1P1 during
system suspend. 1P1 will be turn on depend on USB wakeup is enabled.
Set stop_mode_config bit to turn on 1P1 during system suspend to support USB
host remote wake up or USB device DP/DM wake up.
make shi [Thu, 20 Sep 2012 09:10:20 +0000 (17:10 +0800)]
ENGR00225131-03 MX6 USB: add platform_phy_power_on platform data in head file
IC designer had clarified that 1P1 can be turned off if we do not need support
remote wakeup. So If there is no requirement for USB remote wake up, the 1P1
can be turn off. USB driver will support dynamically turn on(off) 1P1 during
system suspend. 1P1 will be turn on depend on USB wakeup is enabled.
make shi [Thu, 20 Sep 2012 07:14:58 +0000 (15:14 +0800)]
ENGR00225131-02 USB: revert ENGR00221317-02 stop_mode_config patch head file
IC designer had clarified that 1P1 can be turned off if we do not need support
remote wakeup. So If there is no requirement for USB remote wake up, the 1P1
can be turn off. USB driver will support dynamically turn on(off) 1P1 during
system suspend. 1P1 will be turn on depend on USB wakeup is enabled.
make shi [Thu, 20 Sep 2012 07:11:46 +0000 (15:11 +0800)]
ENGR00225131-01 USB: revert ENGR00221317-02 about set stop_mode_config patch
IC designer had clarified that 1P1 can be turned off if we do not need support
remote wakeup. So If there is no requirement for USB remote wake up, the 1P1
can be turn off. USB driver will support dynamically turn on(off) 1P1 during
system suspend. 1P1 will be turn on depend on USB wakeup is enabled.
Ryan QIAN [Mon, 24 Sep 2012 07:25:36 +0000 (15:25 +0800)]
ENGR00225594 mmc: sdhci: remove calling enable clk in interrupt context
There's kernel warning without when insmod WiFi module as follows:
------------[ cut here ]------------
WARNING: at kernel/irq/handle.c:130 handle_irq_event_percpu+0x164/0x180()
irq 55 handler sdhci_irq+0x0/0x988 enabled interrupts
Modules linked in: ar6000
[<800471dc>] (unwind_backtrace+0x0/0xfc) from
[<80072fd0>] (warn_slowpath_common+0x4c/0x64)
[<80072fd0>] (warn_slowpath_common+0x4c/0x64) from
[<8007307c>] (warn_slowpath_fmt+0x30/0x40)
[<8007307c>] (warn_slowpath_fmt+0x30/0x40) from
[<800a9f54>] (handle_irq_event_percpu+0x164/0x180)
[<800a9f54>] (handle_irq_event_percpu+0x164/0x180) from
[<800a9fac>] (handle_irq_event+0x3c/0x5c)
[<800a9fac>] (handle_irq_event+0x3c/0x5c) from
[<800ac2a8>] (handle_fasteoi_irq+0x98/0x148)
[<800ac2a8>] (handle_fasteoi_irq+0x98/0x148) from
[<800a9a2c>] (generic_handle_irq+0x2c/0x38)
[<800a9a2c>] (generic_handle_irq+0x2c/0x38) from
[<80041f60>] (handle_IRQ+0x4c/0xb8)
[<80041f60>] (handle_IRQ+0x4c/0xb8) from
[<80040f8c>] (__irq_svc+0x4c/0xe8)
[<80040f8c>] (__irq_svc+0x4c/0xe8) from
[<800420e4>] (default_idle+0x24/0x28)
[<800420e4>] (default_idle+0x24/0x28) from
[<80042730>] (cpu_idle+0xbc/0xfc)
[<80042730>] (cpu_idle+0xbc/0xfc) from
[<80008904>] (start_kernel+0x248/0x288)
[<80008904>] (start_kernel+0x248/0x288) from
[<10008040>] (0x10008040)
---[ end trace 95ab51b95e0e8e5f ]---
it is caused by calling cancel_delayed_work_sync in sdhci_enable_clk, since
it will call spin_unlock_irq which will possibly enable irq in interrupt
context. if sdhci_enable_clk is called in interrupt context this warning
will be shown.
sdhci_enable_clk will be called in interrupt context in the following path:
sdhci_irq->mmc_signal_sdio_irq->mmc_signal_sdio_irq->sdhci_enable_sdio_irq->...
|____________________interrupt context____________________________________
fix:
Remove calling sdhci_enable_clk in sdhci_enable_sdio_irq. For sdio cards, sdhci
clk will not be disabled, so it is save to remove it.
Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Dong Aisheng <b29396@freescale.com>
ENGR00225534-2 mmc: sdhci: using cancel_work_sync instread of cancel_delayed_work
We recently met an rarely happened sychronization issue which can cause
mmc timeout during transfer as follows:
[ OK ]onfiguring network interfaces...
[ OK ]ctivating swap...
mmc0: Timeout waiting for hardware interrupt.
mmc0: Timeout waiting for hardware interrupt.
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 sending status command, retrying
mmcblk0: error -110 sending stop command, original cmd response 0x900, card status 0xd00
mmcblk0: error -110 transferring data, sector 9981952, nr 16, cmd response 0x900, card status 0xc00
end_request: I/O error, dev mmcblk0, sector 9981952
The root cause is that host uses cancel_delayed_work to cancel the delayed
clock disable work to avoid clock to be disabled if a new cmd
transfer request happens.
However, the work callback may already be running during the excution
of cancel_delayed_work which can not be cancelled and causes
the clock probably still to be disabled during cmd transfer,
then cmd timeout happens.
Using cancel_work_sync instead to wait for the completion of clock disable
first then we can make sure the clock can not be disabled during the cmd
transfer.
BTW, although the original code checks if in interrupt context, however,
it's still not interrupt context safe due to the unsafe platform_clk_ctrl,
so it's ok to directly use cancel_work_sync here and sdhci_enable_clk is
simply not allowed to be called in irq context.
Acked-by: Ryan QIAN <b32804@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com>
Adrian Hunter [Fri, 21 Sep 2012 10:28:42 +0000 (18:28 +0800)]
ENGR00225534-1 mmc: core: move ->request() call from atomic context
mmc_request_done() is sometimes called from interrupt or other atomic
context. Mostly all mmc_request_done() does is complete(), however it
contains code to retry on error, which uses ->request(). As the error
path is certainly not performance critical, this may be moved to the
waiting function mmc_wait_for_req_done().
This allows ->request() to use runtime PM get_sync() and guarantee it
is never in an atomic context.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: Chris Ball <cjb@laptop.org> Acked-by: Ryan QIAN <b32804@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com>
Robby Cai [Wed, 12 Sep 2012 06:32:34 +0000 (14:32 +0800)]
ENGR00224476 pgc: fix display power gating causes PxP processing timeout
The root-cause is PxP need the clock to be on for synchronous reset.
This patch turned on PXP axi clock, and EPDC/LCDIF pix clock, and
EPDC/LCDIF axi clock before power up. The driver codes can guarantee
the clock setting be restored to the one before suspend.
ENGR00223533 - FEC : fix net watchdog timeout due not refreshing TX timers
When do overnight gpu stress test throught nfs, kernel dump as below:
------------[ cut here ]------------
WARNING: at net/sched/sch_generic.c:255 dev_watchdog+0x284/0x2a8()
NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
Modules linked in: galcore imx2_wd_test [last unloaded: galcore]
[<80045854>] (unwind_backtrace+0x0/0xf8) from [<80070c2c>]
(warn_slowpath_common+0x4c/0x64)
<snip>
In sometime, ethernet cannot recover after watchdog timeout which
results in nfs no responding and system hang on.
The patch fixes the way that ->trans_start is refreshed to avoid watchdog
timeout during ethernet status change (such as speed, duplex), and re-init
fec to recover ethernet after watchdog timeout.
Users may call FBIOPUT_VSCREENINFO framebuffer ioctrl to set
a framebuffer's pixel format by specifying bits_per_pixel field
and red/green/blue/transp fields of struct fb_var_screeninfo.
Users may also know a framebuffer's pixel format at which it is
working by calling FBIOGET_VSCREENINFO framebuffer ioctrl, red/
green/blue/transp bitfields of struct fb_var_screeninfo tell the
exact offset and length of each color component in a pixel. This
patch supports RGB24/RGB32/ABGR32 pixel formats with these 2 ioctrls.
To change the default pixel format when initializeing a framebuffer
at the first time, users may add 'fbpix=' option in framebuffer
kernel command line option, for example, 'video=mxcfb0:fbpix=ABGR32'
makes fb0's default pixel format be ABGR32. 'bpp=' option cannot
overwrite 'fbpix=' option, for example, 'video=mxfb0:fbpix=RGB24,
bpp=16' still makes fb0 work at RGB24 by default. To be back
compatible, this patch doesn't change the default pixel formats
(BGR24/BGR32/RGB565) for each bits_per_pixel, if users don't
provide valid 'fbpix=' option.
Liu Ying [Wed, 19 Sep 2012 02:26:25 +0000 (10:26 +0800)]
ENGR00224910 IPUv3 fb:Correct logic to check BGR24 for if= option
This patch corrects the logic to check BGR24 pixel format for
'if=' option in kernel bootup command line of framebuffer.
After applying the patch, users may use 'if=BGR24' to specify
the display data format to be BGR24. For example, 'video=mxcfb0:
dev=lcd,LCD_VIDEO_NAME,if=BGR24' makes IPUv3 output BGR24 data
to fb0's lcd panel.
Daiyu Ko [Wed, 19 Sep 2012 16:15:43 +0000 (11:15 -0500)]
ENGR00221594 Add Dithering algorism support into EPDC driver
Adding Atkinson's dithering alorism implementation into our EPDC
Driver with Y8->Y1 and Y8->Y4 supported. Two EPDC flags have been
added to support the features. EPDC_FLAG_USE_DITHERING_Y1 and
EPDC_FLAG_USE_DITHERING_Y4.
ENGR00224938 HDMI audio: clear HDMI dma done bit before start
HDMI hardware fix: signal of HDMI DMA DONE is hard connected to SDMA
event line. SDMA event is triggered by edge. If the HDMI DMA done is
already 1 before start, there would be no SDMA event being trigged after
HDMI generates another HDMI DONE signal.
In this patch, clear HDMI DONE bit before start HDMI audio DMA.
Adrian Alonso [Thu, 13 Sep 2012 21:43:10 +0000 (16:43 -0500)]
ENGR00224886 board-mx6q-sabreauto: remove camera control lines
* Remove camera control lines, this gpio control lines are used by
other periherals
* GPIO_4_5 correspond to RGMII_INT
* GPIO_3_24 correspond to CSI0_DAT5 parallel tv-in
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 13 Sep 2012 16:26:56 +0000 (11:26 -0500)]
ENGR00224275-2 board-mx6q-sabreauto: remove unsupported ov5640 camera
* Remove unsupported camera device ov5640, there is no
hardware module available for sabreauto target board.
No mechanical connector compability with existing capture
sensor.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Tue, 11 Sep 2012 23:25:42 +0000 (18:25 -0500)]
ENGR00224275-1 board-mx6q-sabreauto: remove unsupported ov3640 camera
* Remove unsupported camera device ov3640, there is no
hardware module available for sabreauto target board.
* No mechanical connector compability with existing capture
sensors.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Josh Boyer [Thu, 18 Aug 2011 11:37:21 +0000 (07:37 -0400)]
perf tools: Fix build against newer glibc
Upstream glibc commit 295e904 added a definition for __attribute_const__
to cdefs.h. This causes the following error when building perf:
util/include/linux/compiler.h:8:0: error: "__attribute_const__"
redefined [-Werror] /usr/include/sys/cdefs.h:226:0: note: this is the
location of the previous definition
Wrap __attribute_const__ in #ifndef as we do for __always_inline.
Robin Gong [Thu, 13 Sep 2012 06:19:41 +0000 (14:19 +0800)]
ENGR00224137 mx6 : restore VDD_PU in resume with the old value before suspend
Before, VDD_PU regulator will be set 1.1V for ever, but now VDD_PU track with
VDD_ARM, so we can not restore with 1.1V when system resume back.We need save
the old value set when power off PU in suspend flow, and then restore it in
resume flow. Signed-off-by: Robin Gong <B38343@freescale.com>
ENGR00224245 HDMI AUDIO: stop/start PCM while unplug,blank/plug, unblank
When unplug, blank happens, HDMI audio can't play properly. So in
driver, audio pcm would be disconnected when event above happens.
However, pulse audio can't process disconnect event properly and if an
blank or unplug event happens, HDMI sink would lost and can't be back
again.
In this patch, instead of disconnecting audio PCM stream, triggering
stop audio pcm while unplug and blank, triggering start again while plug
and unblank if the audio pcm is triggerd stop in the unplug/blank event. Signed-off-by: Chen Liangjun <b36089@freescale.com>
projects / karo-tx-linux.git / log