The CREG block on lpc18xx contains configuration register
for two low power clocks. Support enabling of these two
clocks with a clk driver that access CREG trough the
syscon regmap interface.
These clocks are needed to support peripherals like the
internal RTC on lpc18xx.
Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Fri, 4 Mar 2016 17:36:29 +0000 (09:36 -0800)]
Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull second batch of rockchip clk updates from Heiko Stuebner:
Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.
* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: include downstream muxes into fractional dividers on rk3368
clk: rockchip: set the clock ids for RK3228 HDMI
clk: rockchip: set the clock ids for RK3228 VOP
clk: rockchip: add the tsadc clocks found on rk3228 SoCs
clk: rockchip: add the new clock ids for RK3228 HDMI
clk: rockchip: add the new clock ids for RK3228 VOP
clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
clk: rockchip: fix coding style for clk-cpu.c
clk: rockchip: don't return NULL when registering mmc branch fails
clk: rockchip: don't return NULL when registering inverter fails
clk: rockchip: check grf when waiting pll lock
clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
Sylvain Lemieux [Tue, 23 Feb 2016 19:56:09 +0000 (14:56 -0500)]
clk: lpc32xx: fix compilation warning
Remove the following false positives compilation warning:
- drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized]
- drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate':
warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized]
warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized]
warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized]
Tested using gcc version 4.7.3.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
[sboyd@codeaurora.org: Drop assignment of hw to NULL as return
silences it and is less likely to lead to hiding problems later] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Loc Ho [Mon, 29 Feb 2016 21:15:43 +0000 (14:15 -0700)]
clk: xgene: Add missing parenthesis when clearing divider value
In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.
Signed-off-by: Loc Ho <lho@apm.com> Acked-by: Toan Le <toanle@apm.com> Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Simon Horman [Thu, 3 Mar 2016 02:18:06 +0000 (11:18 +0900)]
clk: renesas: move drivers to renesas directory
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Tue, 1 Mar 2016 18:59:48 +0000 (10:59 -0800)]
clk: hisilicon: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.
Tested-by: Leo Yan <leo.yan@linaro.org> Cc: Bintian Wang <bintian.wang@huawei.com> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 2 Mar 2016 01:30:36 +0000 (17:30 -0800)]
Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX clk updates from Shawn Guo:
The i.MX clock update for 4.6:
- Add the clock driver support for the latest i.MX6 family SoCs
addition - i.MX6QP.
- Clean up the whitespace in i.MX6UL clock driver and add the missing
KPP clock.
- Correct pwm7 clock name in i.MX6UL clock driver.
* tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: add kpp clock for i.MX6UL
clk: imx: whitespace cleanup; no functional change
clk: imx: correct pwm7 clock name in driver for i.MX6UL
clk: imx: Add clock support for imx6qp
Stephen Boyd [Wed, 2 Mar 2016 22:31:42 +0000 (14:31 -0800)]
Merge tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clk updates from Maxime Ripard:
Allwinner clocks additions for 4.6
A bunch of things, mostly:
- Finally switched everything over to OF_CLK_DECLARE, which should remove
orphans clocks entirely
- Reworked the clk-factors to be able to add new parameters
- Improved the error reporting
- A bunch of new clocks for new SoCs.
* tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
clk: sunxi: Add apb0 gates for H3
clk: sunxi: Improve divs_clk error handling and reporting
clk: sunxi: improve divider_clk error handling and reporting
clk: sunxi: improve mux_clk error handling and reporting
clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
clk: sunxi: Remove clk_register_clkdev calls
clk: sunxi: Remove old probe and protection code
clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
clk: sunxi: Make clocks setup functions take const pointer
clk: sunxi: Make clocks setup functions return their clock
clk: sunxi: improve error reporting for the mux clock
clk: sunxi: don't mark sun6i_ar100_data __initconst
clk: sunxi: add bus gates for A83T
clk: sunxi: Add apb0 gates for A83T
clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
clk: sunxi: rewrite sun6i-ar100 using factors clk
clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
clk: sunxi: factors: Drop round_rate from clk ops
clk: sunxi: factors: Support custom formulas
clk: sunxi: factors: Consolidate get_factors parameters into a struct
...
Stephen Boyd [Tue, 1 Mar 2016 18:51:42 +0000 (10:51 -0800)]
clk: ti: Fix some errors found by static checkers
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)
The last one looks like a real bug because we don't return an
error on allocation failure.
Cc: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tony Lindgren [Fri, 26 Feb 2016 17:35:05 +0000 (09:35 -0800)]
clk: ti: Add support for dm814x ADPLL
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.
Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.
Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.
Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Archit Taneja [Sun, 28 Feb 2016 10:07:17 +0000 (15:37 +0530)]
clk: qcom: Fix pre-divider usage for pixel RCG
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.
Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.
Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.
Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 19:14:25 +0000 (11:14 -0800)]
simplefb: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Cc: Hans de Goede <hdegoede@redhat.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: <linux-fbdev@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:49:23 +0000 (17:49 -0800)]
clk: ti: Update for of_clk_get_parent_count() returning unsigned int
Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.
Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:44:27 +0000 (17:44 -0800)]
clk: sunxi: Use proper type for of_clk_get_parent_count() return value
The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:36:51 +0000 (17:36 -0800)]
clk: h8300: Remove impossible check for of_clk_get_parent_count()
The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Fri, 19 Feb 2016 23:52:32 +0000 (15:52 -0800)]
clk: Make of_clk_get_parent_count() return unsigned ints
Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.
Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.
"status = "disabled";
are still activated.
Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.
clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
cpg_div6_clock_set_rate() only programs the new divisor if the clock
isn't stopped. If the clock is stopped, it will update the cached
divisor value only, which will be programmed into the clock registers
when enabling the clock later.
However, cpg_div6_clock_recalc_rate() reads the divisor from the clock
registers instead of using the cached value, leading to an incorrect
result if the clock is currently stopped.
Make cpg_div6_clock_recalc_rate() use the cached value to fix this.
Shawn Lin [Fri, 26 Feb 2016 01:25:52 +0000 (09:25 +0800)]
clk: skip unnecessary set_phase if nothing to do
Let's compare the degrees from clk_set_rate with
clk->core->phase. If the requested degrees is already
there, skip the following steps.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[sboyd@codeaurora.org: s/drgrees/degrees/ in commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1
Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Simon Horman [Tue, 23 Feb 2016 00:57:31 +0000 (09:57 +0900)]
clk: shmobile: Remove ARCH_SHMOBILE_MULTI
As of 9b5ba0df4ea4 ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Thu, 25 Feb 2016 23:18:12 +0000 (15:18 -0800)]
Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver changes from Sylwester Nawrocki:
Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.
* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
clk/samsung: exynos5433: add pclk_decon clock
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
Kevin Smith [Thu, 11 Feb 2016 16:54:00 +0000 (16:54 +0000)]
clk: mvebu: Move corediv config to mvebu config
The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct. Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.
This also enables corediv on Armada 375 and 38X, which was
previously missing.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kevin Smith [Thu, 11 Feb 2016 16:53:52 +0000 (16:53 +0000)]
clk: mvebu: Remove corediv clock from Armada XP
There is no corediv clock on Armada XP, so this is unnecessary.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Linus Walleij [Wed, 24 Feb 2016 08:39:11 +0000 (09:39 +0100)]
clk: versatile: sp810: support reentrance
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
(show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
(dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
(time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
(start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com> Cc: Pawel Moll <pawel.moll@arm.com> Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver" Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 27 Jan 2016 22:17:00 +0000 (14:17 -0800)]
clk: Get rid of HAVE_MACH_CLKDEV
This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.
clk: qcom: Add IPQ4019 Global Clock Controller support
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
the commit log a bit] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Sudip Mukherjee [Tue, 23 Feb 2016 09:30:03 +0000 (15:00 +0530)]
clk: shmobile: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper devm_add_action_or_reset() and return directly
as we know that the cleanup has been done by this helper.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Joachim reports that this commit breaks lpc18xx boot. This is
because the hardware has circular clk topology where PLLs can
feed into dividers and the same dividers can feed into the PLLs.
The hardware is designed this way so that you can choose to put
the divider before the PLL or after the PLL depending on what you
configure to be the parent of the divider and what you configure
to be the parent of the PLL.
So let's drop this patch for now because we have hardware that
actually has loops. A future patch could check for circular
parents when we change parents and fail the switch, but that's
probably best left to some debugging Kconfig option so that we
don't suffer the sanity checking cost all the time.
Reported-by: Joachim Eastwood <manabian@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Dinh Nguyen [Mon, 22 Feb 2016 21:52:46 +0000 (15:52 -0600)]
clk: socfpga: allow for multiple parents on Arria10 periph clocks
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.
Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Sat, 20 Feb 2016 11:24:26 +0000 (13:24 +0200)]
clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs
Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Sat, 20 Feb 2016 11:12:57 +0000 (13:12 +0200)]
clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
As the code in this file is being executed within irq context in some
cases, we must avoid the clk_get_rate which uses mutex internally.
Switch the code to use clk_hw_get_rate instead which is non-locking.
This fixes an issue where PM runtime will hang the system if enabled
with a serial console before a suspend-resume cycle.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
so it is built also on ARMv7. This does not bring any kind of benefit.
There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
multi_v7 for ARMv7).
Instead build clock drivers only for respective SoC's architecture.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Andre Przywara [Tue, 16 Feb 2016 10:46:08 +0000 (10:46 +0000)]
clk: sunxi: Improve divs_clk error handling and reporting
We catch errors in the base clock registration, failure to ioremap
and failures in the final of_clk_add_provider() call.
Also we unmap the registers when we need to rollback.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Tue, 16 Feb 2016 10:46:07 +0000 (10:46 +0000)]
clk: sunxi: improve divider_clk error handling and reporting
We now report a failing ioremap, failing output names parsing,
failures in table registration and in the final step.
Also there was a bug where clk_register_divider_table() would return
an ERR_PTR value instead of NULL, which we were checking for.
We now implement proper rollback in case of an error.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Tue, 16 Feb 2016 10:46:06 +0000 (10:46 +0000)]
clk: sunxi: improve mux_clk error handling and reporting
We now catch and report a failing ioremap, also a failure in the final
step of the clock registration is now handled and reported.
Also warnings are turned into errors.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Stephen Boyd [Fri, 19 Feb 2016 03:07:44 +0000 (19:07 -0800)]
clk: gpio: Really allow an optional clock= DT property
We mis-merged the original patch from Russell here and so the
patch went almost all the way, except that we still failed to
probe when there wasn't a clocks property in the DT node. Allow
that case by making a negative value from
of_clk_get_parent_count() into "no parents", like the original
patch did.
Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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