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11 years agoENGR00233051-02 Mx6 USB: msl headfile for OTG modulization
make shi [Thu, 8 Nov 2012 07:23:33 +0000 (15:23 +0800)]
ENGR00233051-02 Mx6 USB: msl headfile for OTG modulization

MSL headfile part change

-Add and remove some function define in usb.h

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00233051-01 Mx6 USB: configure change for OTG modulization
make shi [Thu, 8 Nov 2012 07:18:50 +0000 (15:18 +0800)]
ENGR00233051-01 Mx6 USB: configure change for OTG modulization

- Add USB_FSL_ARC_OTG configuration to imx6_defconfig and imx6s_defconfig,
  the default configuration is selected as "y"
- add related USB_FSL_ARC_OTG configuration to Makefile
- add related USB_FSL_ARC_OTG configuration to Kconfig

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00233427 ASRC: add interface to modify ASRC input/output watermark
Chen Liangjun [Tue, 13 Nov 2012 08:43:25 +0000 (16:43 +0800)]
ENGR00233427 ASRC: add interface to modify ASRC input/output watermark

In this patch, add interface to modify ASRC input/output watermark.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00233380 IPUv3:Warn on sub-CPMEM EBA0 unalignment case
Liu Ying [Tue, 13 Nov 2012 06:42:27 +0000 (14:42 +0800)]
ENGR00233380 IPUv3:Warn on sub-CPMEM EBA0 unalignment case

IPUv3 CPMEM EBA sets buffer start address. EBA should be 8-byte
aligned according to IPUv3 spec. This patch contains code change
only to warn on alternative CPMEM entry's EBA0 unalignment case.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 1a2f3dc6340d5cf93f2e4bcd5a9d4395fcc18cf1)

11 years agoENGR00232945-4: CAAM: enable SNVS config
Terry Lv [Thu, 8 Nov 2012 10:01:02 +0000 (18:01 +0800)]
ENGR00232945-4: CAAM: enable SNVS config

Enable SNVS config.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00232945-3: CAAM: Add core of SNVS state handler module
Steve Cornelius [Thu, 8 Nov 2012 07:40:51 +0000 (00:40 -0700)]
ENGR00232945-3: CAAM: Add core of SNVS state handler module

Add core of SNVS state handler module.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00232945-2: CAAM: Add SNVS state handler startup
Steve Cornelius [Thu, 8 Nov 2012 07:39:05 +0000 (00:39 -0700)]
ENGR00232945-2: CAAM: Add SNVS state handler startup

Add SNVS state handler startup to CAAM controller driver.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00232945-1: CAAM: Add build environment for CAAM/SNVS handlers
Steve Cornelius [Thu, 8 Nov 2012 07:33:13 +0000 (00:33 -0700)]
ENGR00232945-1: CAAM: Add build environment for CAAM/SNVS handlers

Add build environment for CAAM/SNVS security violation handlers.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00233056 ALSA: adjust dma wm & buffersize configuration strategy
Nicolin Chen [Fri, 9 Nov 2012 07:44:33 +0000 (15:44 +0800)]
ENGR00233056 ALSA: adjust dma wm & buffersize configuration strategy

 Previously SSI/ESAI/SPDIF used one same-sized buffers and watermark(the
WM in the title) for every alsa driver.

 This patch allow each driver config its own buffer size and watermark,
which is obviously more flexible.

 Also, it sets SSI's buffersize from 256k to 64k.

Signed-off-by: Nicolin Chen <b42378@freescale.com>
11 years agoENGR00232528 - IEEE1588:imx6:Upgrade driver to support IXXAT stack V1.05.03
Fugang Duan [Mon, 29 Oct 2012 10:00:09 +0000 (18:00 +0800)]
ENGR00232528 - IEEE1588:imx6:Upgrade driver to support IXXAT stack V1.05.03

Upgrade drivers to support IXXAT IEEE1588 stack V1.05.03.
Ptp message protocol support IPv4, IPv6, and IEEE802.3 L2.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration.
Fugang Duan [Thu, 20 Sep 2012 07:26:49 +0000 (15:26 +0800)]
ENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration.

In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
1. Disable on-chip pull-up, pull-down, and keeper
2. Disable hysteresis
3. Speed = 100 MHz
4. Slew rate = fast

The optimizition make the bias point match the optimum point, which
can maximize design margin.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00232660 EPDC: Wrong panel loaded at boot
Michael Minnick [Tue, 6 Nov 2012 19:21:50 +0000 (13:21 -0600)]
ENGR00232660 EPDC: Wrong panel loaded at boot

The wrong EPDC panel can be loaded at boot time if the machine
board file has multiple panel entries with the same video mode
parameter values. To reproduce, select a particular panel with
u-boot kernel command line parameters, for example:
video=mxcepdcfb:XYZZY

Add panel XYZZY to arch/arm/mach-mx6/board-mx6sl_evk.c after
an existing entry. Use the same video mode parameter settings
as the existing entry. On boot, the existing panel will be loaded
instead of the XYZZY panel because it comes earlier in the list
and happens to have the same video mode parameter values.

Solution: If the video mode parameter settings specified in
the call to msc_epdc_fb_set_par() match those of the panel
already loaded by mxc_epdc_fb_probe(), don't execute a
search for a new matching panel.

Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
11 years agoENGR00232930 Added default video mode check, make sure it is a CEA mode.
Sandor Yu [Thu, 8 Nov 2012 08:24:10 +0000 (16:24 +0800)]
ENGR00232930 Added default video mode check, make sure it is a CEA mode.

When system bootup without HDMI plugin, the default modelist
and default video mode will create.
Match default video mode in default CEA modelist, make sure
default video mode is a CEA mode.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00231273-02 mmc: sdhci: fix failed to call platform exit on removal
Ryan QIAN [Fri, 26 Oct 2012 02:13:34 +0000 (10:13 +0800)]
ENGR00231273-02 mmc: sdhci: fix failed to call platform exit on removal

Since sdhci_pltfm_data is stored in platform_device_id, but in
sdhci_pltfm_remove, it tried to get sdhci_pltfm_data directly from
pdev->dev.platform_data. It will result that it could not get the correct
sdhci_pltfm_data, so that platform exit will not be called on sdhci module's
removal.

Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00231273-01 mmc: sdhci: modularize sdhci driver
Ryan QIAN [Fri, 26 Oct 2012 02:11:22 +0000 (10:11 +0800)]
ENGR00231273-01 mmc: sdhci: modularize sdhci driver

Export sdhci_request to fix build error.

Here's the error message:
ERROR: "sdhci_request" [drivers/mmc/host/sdhci-platform.ko] undefined!

Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00232583 Mx6 USB host: Set HCD_FLAG_HW_ACCESSIBLE flag after clock gate
make shi [Tue, 6 Nov 2012 07:52:24 +0000 (15:52 +0800)]
ENGR00232583 Mx6 USB host: Set HCD_FLAG_HW_ACCESSIBLE flag after clock gate

There is a USB hang issue when do system suspend/resume test with a USB
device plug in. The issue is caused by USB host driver accessing register
when clock is off. Currently set HCD_FLAG_HW_ACCESSIBLE bit before open
clock in ehci_fsl_bus_resume, it cause accessing register without clock.
So we should change the code call order to avoid driver access register
without clock.

- Set HCD_FLAG_HW_ACCESSIBLE software flag after HW clock turn on
- remove some unnecessary code in ehci_fsl_pre_irq

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00232586 mx6: increase PUPSCR to make sure LDO is ready for resume
Anson Huang [Tue, 6 Nov 2012 22:47:26 +0000 (17:47 -0500)]
ENGR00232586 mx6: increase PUPSCR to make sure LDO is ready for resume

Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00231266-4: board-mx6q_sabreauto adv7280 csi-tx slave address
Adrian Alonso [Wed, 24 Oct 2012 16:58:53 +0000 (11:58 -0500)]
ENGR00231266-4: board-mx6q_sabreauto adv7280 csi-tx slave address

* Pass csi-tx slave address for adv7280 chipset

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00231266-3: adv7280_mipi_tvin add regulator support
Adrian Alonso [Thu, 25 Oct 2012 20:15:26 +0000 (15:15 -0500)]
ENGR00231266-3: adv7280_mipi_tvin add regulator support

* Add regulator support
  Set regulator voltage and enable them
  On remove callback disable regulators
* Add callbacks for target platform custom
  reset, power up/down and io pads configuration

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00231266-2: adv7280_mipi_tvin add i2c dummy client for csi config
Adrian Alonso [Wed, 24 Oct 2012 16:37:11 +0000 (11:37 -0500)]
ENGR00231266-2: adv7280_mipi_tvin add i2c dummy client for csi config

* Add i2c dummy client for csi-tx register map config
* adv7280 csi-tx reg banks are mapped in a different
  memory map and respond to a different i2c slave address
  that user can configure
* Add default config helper function
* Override slave csi-tx address if user provides a different
  value.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00231266-1: fsl_devices add csi_tx_addr
Adrian Alonso [Wed, 24 Oct 2012 16:32:34 +0000 (11:32 -0500)]
ENGR00231266-1: fsl_devices add csi_tx_addr

* Add csi_tx_addr, so it can override slave addr
  for adv7280 tvin decoder device

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00231773-9 ASRC: increace convert speed while in ideal mode
Chen Liangjun [Wed, 31 Oct 2012 04:52:48 +0000 (12:52 +0800)]
ENGR00231773-9 ASRC: increace convert speed while in ideal mode

Increase convert speed while ASRC is working on ideal ratio mode to
satisfy asrc plugin's timing request.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-8 ASRC: prevent user app from processing input/output processing
Chen Liangjun [Wed, 31 Oct 2012 09:27:23 +0000 (17:27 +0800)]
ENGR00231773-8 ASRC: prevent user app from processing input/output processing

To finish a buffer convert in ASRC, user should 1. prepare input buffer,
2. prepare output buffer 3. wait for output buffer's completion 4.wait
for input buffer's comletion. The flow make user application ugly.

In this patch, pack steps above to 1 stop: ASRC_CONVERT.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-7 DMA: add interface to trigger SDMA event pending bit
Chen Liangjun [Mon, 29 Oct 2012 07:38:26 +0000 (15:38 +0800)]
ENGR00231773-7 DMA: add interface to trigger SDMA event pending bit

Add interface in header file to call sdma event pending trigger
function.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-6 SDMA: add event pending trigger interface
Chen Liangjun [Mon, 29 Oct 2012 07:36:24 +0000 (15:36 +0800)]
ENGR00231773-6 SDMA: add event pending trigger interface

When SDMA is use for periphal data transfer, dma request is trigger by
FIFO level. If the SDMA is started after the start of periphal, SDMA
would miss the first pulse and be not able to trigger itself.

In this patch, add interface to trigger a dma request manully.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-5 ASRC: use poll mode to receive last period of ASRC data
Chen Liangjun [Wed, 31 Oct 2012 03:11:26 +0000 (11:11 +0800)]
ENGR00231773-5 ASRC: use poll mode to receive last period of ASRC data

ASRC driver use DMA to transfer data from ASRC output FIFO to memory.
However, DMA way require the data number in ASRC output FIFO being larger
than watermark level. Thus a dma request can trigger a DMA burst. For
the last period of output data, its number is possiblely less than output
FIFO watermark level. In this case, the output DMA would pending for the
last period of output data until timeout.

In this patch:
1 divide expected output data length into 2 parts: DMA part
and poll part. Using DMA to get the DMA part data and poll mode to
get the poll part.
2 to prevent user from processing these 2 parts above, kernel
buffers would be untouchable. User application only need send its data
buffer address to driver instead of query the kernel buffer.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-4 ASRC: use scatter list and stall bit for asrc convert
Chen Liangjun [Fri, 26 Oct 2012 09:43:30 +0000 (17:43 +0800)]
ENGR00231773-4 ASRC: use scatter list and stall bit for asrc convert

In the origin code, ASRC driver use cyclic way to process DMA task
transfering data to/from ASRC input/output FIFO. In this case, it is
necessary that user application should promise that the input buffer
flow is continuous. If not, there would be 0 data be inserted into data
flow. The output data would be noisy.

In this patch,
1 use scatter list instead of cyclic SDMA: with scatter list,
SDMA would stop when the applied scatter list nents are finished.
2 set stall bit for ASRC "memory->ASRC->memory" convert to stop
ASRC convert when input data is not send into ASRC input FIFO in time.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-3 ASRC: use kzalloc to allocate buffer to support scatterlist
Chen Liangjun [Fri, 26 Oct 2012 07:10:09 +0000 (15:10 +0800)]
ENGR00231773-3 ASRC: use kzalloc to allocate buffer to support scatterlist

For ASRC's "memory -> ASRC -> memory" using, new driver would support
model below: user input one buffer into ASRC and an corresponding output
buffer would be poped out. There is no timing requirement between this
input buffer and next input buffer. Thus driver would not use the cyclic
way to config SDMA and scatterlist is used. buffer allocated by
dma_alloc_coherent() can't support scatterlist well.

In this patch, use kzalloc to allocate buffer to support scatterlist.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-2 ASRC: add work struct for asrc output data receive
Chen Liangjun [Fri, 26 Oct 2012 05:42:35 +0000 (13:42 +0800)]
ENGR00231773-2 ASRC: add work struct for asrc output data receive

SDMA driver can't promise receive all output data generated. Cause when
the data in output FIFO is less than ASRC output FIFO watermark, there
would be no DMA request generated and thus no SDMA transfer would
happens.

In this patch, add work struct to support ASRC driver receive last part
of data in OUTPUT FIFO in polling way.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00231773-1 ASRC: remove queue operation in ASRC driver
Chen Liangjun [Fri, 26 Oct 2012 08:07:41 +0000 (16:07 +0800)]
ENGR00231773-1 ASRC: remove queue operation in ASRC driver

According to ASRC memory->ASRC->memory requirement, driver should
satisfy the feature below: user application would passed into one buffer
and waiting until the output buffer is generated. In this case, only one
buffer is on processing and it is no necessary to use the queue to do
the convert. What is worse, queue operation would make the ASRC driver
hard to understand and maintain.

In this patch, remove the queue operation in ASRC driver.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00232424 LDB:Support WXGA@60 video mode
Liu Ying [Mon, 5 Nov 2012 07:58:17 +0000 (15:58 +0800)]
ENGR00232424 LDB:Support WXGA@60 video mode

This patch adds WXGA(1280x800@60) video mode
support to driver CHIMEI WXGA LVDS panel.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 653fbb0cd709bf25942c29c0695ecc4af6987e24)

11 years agoENGR00232327 MX6SL-Optimize board level suspend power
Ranjani Vaidyanathan [Fri, 2 Nov 2012 21:11:38 +0000 (16:11 -0500)]
ENGR00232327 MX6SL-Optimize board level suspend power

Improve the board level suspend power by configuring
various IOMUX pads to low power state.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00232326 MX6x-Fix incorrect I2C bitrate
Ranjani Vaidyanathan [Thu, 25 Oct 2012 20:51:51 +0000 (15:51 -0500)]
ENGR00232326 MX6x-Fix incorrect I2C bitrate

IPG_PERCLK is the parent of I2C. I2C needs a minimum of
12.8MHz as its input clock to achieve 400KHz speed. Hence
change the IPG_PERCLK speed accordingly.
MX6DQ/MX6DL - Set IPG_PERCLK at 22MHz (sourced from IPG_CLK)
MX6SL - Set IPG_PERCLK to 24MHz(Sourced from 24MHz XTAL).

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00225875-2 i.MX6Q/Solo Sabreauto Bluetooth H4 fix uart rx timeouts.
Israel Perez [Wed, 31 Oct 2012 22:13:36 +0000 (17:13 -0500)]
ENGR00225875-2 i.MX6Q/Solo Sabreauto Bluetooth H4 fix uart rx timeouts.

Bluetooth H4 protocol is very susceptible to data reception timeouts.
DMA transfer only happen when ICD or AGTIM interrutps are trigger.
ICD only happen when a N idle frames are present on rx line
and rx FIFO is empty.
Meanwhile Aging timer is trigger when data in FIFO was been sitting for a
period of 8 frames.
This patch enable both in order to dispatch data as fast is possible only
when the select uart have enable DMA flag.

Signed-off-by: Israel Perez <B37753@freescale.com>
11 years agoENGR00225875-1 i.MX6Q/Solo SabreAuto Infineon Bluetooth uart3 config
Israel Perez [Wed, 31 Oct 2012 22:06:44 +0000 (17:06 -0500)]
ENGR00225875-1 i.MX6Q/Solo SabreAuto Infineon Bluetooth uart3 config

Configure MUX settings for bluetooth operation over UART3.
Enable RTS,CTS and DMA only for uart3.
Affected files :
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabreauto.h
arch/arm/mach-mx6/board-mx6solo_sabreauto.h
arch/arm/plat-mxc/include/mach/iomux-mx6q.h
On behalf of Francisco Munoz <francisco.munoz@freescale.com>.
Some modification are needed also on hciattach tool.

Signed-off-by: Israel Perez <B37753@freescale.com>
11 years agoENGR00232000: Fix "dmaengine: failed to get dma1chan0: (-22)" when boot
Robby Cai [Fri, 2 Nov 2012 07:58:40 +0000 (15:58 +0800)]
ENGR00232000: Fix "dmaengine: failed to get dma1chan0: (-22)" when boot

The log from [MX6DL/S_SD]:
...
mxc_sdc_fb mxc_sdc_fb.1: register mxc display driver ldb
dmaengine: failed to get dma1chan0: (-22)
dmaengine: failed to get dma1chan1: (-22)
dmaengine: failed to get dma1chan2: (-22)
dmaengine: failed to get dma1chan3: (-22)
dmaengine: failed to get dma1chan4: (-22)
dmaengine: failed to get dma1chan5: (-22)
dmaengine: failed to get dma1chan6: (-22)
dmaengine: failed to get dma1chan7: (-22)
dmaengine: failed to get dma1chan8: (-22)
dmaengine: failed to get dma1chan9: (-22)
dmaengine: failed to get dma1chan10: (-22)
dmaengine: failed to get dma1chan11: (-22)
dmaengine: failed to get dma1chan12: (-22)
dmaengine: failed to get dma1chan13: (-22)
dmaengine: failed to get dma1chan14: (-22)
dmaengine: failed to get dma1chan15: (-22)
...

It happens when there are many DMA-engine drivers in the system and
dmaengine_get() is called. dmaengine_get() will call dma_chan_get(), which will
call device_alloc_chan_resources() literally on channels of available dma
drivers unless reach -ENODEV. device_alloc_chan_resources() is implemented
in the individual dma drivers, which could return -EINVAL rather than -ENODEV,
then the above messages print out (doesn't hurt, however).

Indeed, the dmaengine_get() and dmaengine_put() is not needed and thus removed.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00231778 MX6 ESAI: Adjust channel support capability of cpu/codec dai
Lionel Xu [Wed, 31 Oct 2012 08:40:37 +0000 (16:40 +0800)]
ENGR00231778 MX6 ESAI: Adjust channel support capability of cpu/codec dai

To adjust the channel support capability, codec dai does not support mono
playback and record, while esai dai does, thus making the whole audio
codec only support stereo and above channel playback/record.

Signed-off-by: Lionel Xu <R63889@freescale.com>
11 years agoENGR00231826 imx esdhc: Add the DMA mask for esdhc device register.
Xinyu Chen [Wed, 31 Oct 2012 06:41:37 +0000 (14:41 +0800)]
ENGR00231826 imx esdhc: Add the DMA mask for esdhc device register.

We must set the DMA mask for esdhc device.
To avoid the following crash when we do not have highmem pages:

[<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
[<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
[<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
[<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>]
[<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
[<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
[<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
[<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
[<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
[<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
[<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
[<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
[<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
[<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
[<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
[<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
[<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
[<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
[<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
[<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
[<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
[<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]

When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.

Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
11 years agoENGR00232087-2 VPU: Fix suspend/resume bugs
Hongzhang Yang [Thu, 1 Nov 2012 11:34:26 +0000 (19:34 +0800)]
ENGR00232087-2 VPU: Fix suspend/resume bugs

1. Fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang
after resume from suspend during video playback. 20%

2. Fix ENGR00231830 [MX6DL/S_SD] VPU: VPU encode can't
finish and print "VPU blocking: timeout." if suspend/resume. 100%

Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
11 years agoENGR00232087-1 MX6: Enable PU LDO gating.
Hongzhang Yang [Thu, 1 Nov 2012 11:26:44 +0000 (19:26 +0800)]
ENGR00232087-1 MX6: Enable PU LDO gating.

1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;

2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%

Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
11 years agoENGR00232005 mtd: fix the overflow of big mtd partitions
Huang Shijie [Thu, 1 Nov 2012 06:23:25 +0000 (14:23 +0800)]
ENGR00232005 mtd: fix the overflow of big mtd partitions

When the kernel parses the following cmdline

#mtdparts=gpmi-nand:16m(boot),16m(kernel),1g(home),4g(test),-(usr)

for a big nand chip Micron MT29F64G08AFAAAWP(8GB), we got the following wrong
result:

.............................................
"mtd: partition size too small (0)"
.............................................

We can not get any partition.

The "4g(test)" partition triggers a overflow of the "size". The memparse()
returns 4g to the "size", but the size is "unsigned long" type, so a overflow
occurs, the "size" becomes zero in the end.

This patch changes the "size"/"offset" to "unsigned long long" type,
and replaces the UINT_MAX with ULLONG_MAX for macros SIZE_REMAINING and
OFFSET_CONTINUOUS.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00231965 MX6 USB CV 3.0 test fail
Tony LIU [Thu, 1 Nov 2012 02:15:18 +0000 (10:15 +0800)]
ENGR00231965 MX6 USB CV 3.0 test fail

- For USB CV 3.0 test, the gap between the ACK of set_address and
  the subsequent setup packet may be very little, say 500us, and
  if the latency we handle the ep completion is greater than this
  gap, there is no response to the subsequent packet. It will
  cause CV test fail

- There is another way to set the address, it should set the bit 24
  to 1 with the right address, and then IC controller will set the
  address when the IN req complete instead of SW do it. It is more
  fast so it can fix the CV 3.0 test fail issue

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agomtd: support ONFI multi lun NAND
Matthieu CASTET [Mon, 19 Mar 2012 14:35:25 +0000 (15:35 +0100)]
mtd: support ONFI multi lun NAND

With onfi a flash is organized into one or more logical units (LUNs).
A" logical unit (LUN) is the minimum unit that can independently execute
commands and report status.

Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.

Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.

Artem: split long line on 2 shorter ones.

Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agomtd: nand_flash_detect_onfi propagate busw info
Matthieu CASTET [Sun, 26 Jun 2011 16:26:55 +0000 (18:26 +0200)]
mtd: nand_flash_detect_onfi propagate busw info

there is a bug in nand_flash_detect_onfi, busw need to be passed
by pointer to return it.

Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <dedekind1@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00231910 PU regulator: do not disable PU regulator
Robin Gong [Wed, 31 Oct 2012 13:41:16 +0000 (21:41 +0800)]
ENGR00231910 PU regulator: do not disable PU regulator

If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding  on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP.
Signed-off-by: Robin Gong <b38343@freescale.com>
11 years agoENGR00231595 spdif: improve spdif driver
Gary Zhang [Tue, 30 Oct 2012 06:52:30 +0000 (14:52 +0800)]
ENGR00231595 spdif: improve spdif driver

add clk operation in mxc_pb_spdif_put function

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00231063 Sabreauto: fix share pins SD Card and NFC
Alejandro Sierra [Wed, 24 Oct 2012 20:32:37 +0000 (15:32 -0500)]
ENGR00231063 Sabreauto: fix share pins SD Card and NFC

SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00230538-10: imx6: CAAM: enable secure memory and sm test in defconfig
Terry Lv [Mon, 29 Oct 2012 06:18:25 +0000 (14:18 +0800)]
ENGR00230538-10: imx6: CAAM: enable secure memory and sm test in defconfig

Enable secure memory and sm test in defconfig.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-9: CAAM: Add example/test component for CAAM-SM
Steve Cornelius [Fri, 19 Oct 2012 21:51:48 +0000 (14:51 -0700)]
ENGR00230538-9: CAAM: Add example/test component for CAAM-SM

Add example/test component for CAAM-SM.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-8: CAAM: Add CAAM Secure Memory / Keystore API
Steve Cornelius [Fri, 19 Oct 2012 21:50:55 +0000 (14:50 -0700)]
ENGR00230538-8: CAAM: Add CAAM Secure Memory / Keystore API

Add CAAM Secure Memory / Keystore API.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-7: CAAM: Add build configuration for SM API
Steve Cornelius [Fri, 19 Oct 2012 21:48:59 +0000 (14:48 -0700)]
ENGR00230538-7: CAAM: Add build configuration for SM API

This adds build configuration information for the prototype CAAM
Secure Memory API, and the example/test module that accompanies it.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-6: CAAM: Detection and initialization for secure memory.
Steve Cornelius [Fri, 19 Oct 2012 21:47:45 +0000 (14:47 -0700)]
ENGR00230538-6: CAAM: Detection and initialization for secure memory.

Detection and initialization for secure memory.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-5: CAAM: Add SM register defs
Steve Cornelius [Fri, 19 Oct 2012 21:43:41 +0000 (14:43 -0700)]
ENGR00230538-5: CAAM: Add SM register defs

Add SM register defs, and expanded driver-private storage.

These add changes to the driver private areas for the CAAM
controller and CAAM Secure Memory subsystems, and expand register
definitions to include the Secure Memory subsystems as reflected
in multiple areas (controller, rings, secure memory itself).

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-4: CAAM: Add Blob command bitdefs.
Steve Cornelius [Fri, 19 Oct 2012 21:37:12 +0000 (14:37 -0700)]
ENGR00230538-4: CAAM: Add Blob command bitdefs.

Add Blob command bitdefs.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-3: CAAM: Add SNVS HP and LP register definitions
Steve Cornelius [Fri, 19 Oct 2012 21:35:25 +0000 (14:35 -0700)]
ENGR00230538-3: CAAM: Add SNVS HP and LP register definitions

Add SNVS HP and LP register definitions.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-2: CAAM: Add Secure Memory and SNVS properties
Steve Cornelius [Fri, 19 Oct 2012 20:27:24 +0000 (13:27 -0700)]
ENGR00230538-2: CAAM: Add Secure Memory and SNVS properties

Add Secure Memory and SNVS properties to MX6 configuration.

Previous configurations of MX6 platform device definition lacked
specific propeties for CAAM Secure Memory and SNVS. Added these
properties to define register ranges for both entities.

Also corrected the name for the offset of the address range for
CAAM Secure Memory to more accurately reflect it's purpose.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection
Steve Cornelius [Fri, 19 Oct 2012 20:18:37 +0000 (13:18 -0700)]
ENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection

3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock

IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00231321-2 wm8962: enhance audio driver
Gary Zhang [Fri, 26 Oct 2012 08:16:56 +0000 (16:16 +0800)]
ENGR00231321-2 wm8962: enhance audio driver

1. correct indent issue
2. when driver is unloaded, remove disable clock operateion and free irq

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00231321-1 mx6: remove wm8958 in imx6_defconfig
Gary Zhang [Fri, 26 Oct 2012 08:10:38 +0000 (16:10 +0800)]
ENGR00231321-1 mx6: remove wm8958 in imx6_defconfig

not set wm8958 codec as builtin in imx6_defconfig

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00230981-3 pfuze: add suspend voltage set interface
Robin Gong [Fri, 26 Oct 2012 11:19:43 +0000 (19:19 +0800)]
ENGR00230981-3 pfuze: add suspend voltage set interface

Implement set_suspend_voltage for buck switch of PF100, and set_suspend_enable
/set_suspend_disable interface for LDO(VGENx).
Signed-off-by: Robin Gong <b38343@freescale.com>
11 years agoENGR00230981-2 pfuze:standby voltage increase for PFM
Robin Gong [Wed, 24 Oct 2012 10:28:59 +0000 (18:28 +0800)]
ENGR00230981-2 pfuze:standby voltage increase for PFM

There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set  VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common  "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>
11 years agoENGR00231331 mtd: gpmi: add kernel command line to enable gpmi in arm2 board
Huang Shijie [Fri, 26 Oct 2012 08:04:03 +0000 (16:04 +0800)]
ENGR00231331 mtd: gpmi: add kernel command line to enable gpmi in arm2 board

In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00231104 i.MX cpufreq: add scaling_available_freqs attribute
Lin Fuzhen [Thu, 25 Oct 2012 06:19:24 +0000 (14:19 +0800)]
ENGR00231104 i.MX cpufreq: add scaling_available_freqs attribute

Add scaling_available_freqs attribute in cpufreq for i.MX
can get cpufreq table info with:

cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
996000 792000 396000

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO
make shi [Thu, 18 Oct 2012 07:59:18 +0000 (15:59 +0800)]
ENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO

The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.

- Implement vdd3p0 regulator enable and disable function to support
  enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
  to 3.2V during system boot up. And disable the LDO before system
  enter suspend and enable the LDO again after system resume.

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00230910 IPU: wrong display to downsize large resolution frame on split mode
Wayne Zou [Wed, 24 Oct 2012 01:36:00 +0000 (09:36 +0800)]
ENGR00230910 IPU: wrong display to downsize large resolution frame on split mode

Fix bug: IPU IC resize ratio overflow when downsizing large resolution frame
using split mode, for example downsize 4080x2720 frame into 1920x1080 frame.
Otherwise, the downsized frame is wrong.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00230923 Revert " input: FSL MPR121 capacitive touch button."
Zhang Jiejing [Wed, 24 Oct 2012 04:49:23 +0000 (12:49 +0800)]
ENGR00230923 Revert " input: FSL MPR121 capacitive touch button."

There was a mpr121_touchkey.c driver already upstream,
the orignall driver by 2.6.35 kernel development
should be removed to avoid duplicate.

This reverts commit 3d6df22ad54a14bc8cebb7753c36f7b3cd811665.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agoENGR00230920-3 HDMI AUIDO: export symbol in HDMI core driver
Chen Liangjun [Wed, 24 Oct 2012 04:46:53 +0000 (12:46 +0800)]
ENGR00230920-3 HDMI AUIDO: export symbol in HDMI core driver

Export symbol in HDMI core driver to support HDMI AUDIO codec driver's
loadable module build.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00230920-2 HDMI AUDIO: export gloable variable in platform driver
Chen Liangjun [Wed, 24 Oct 2012 04:45:16 +0000 (12:45 +0800)]
ENGR00230920-2 HDMI AUDIO: export gloable variable in platform driver

Export gloable variable in HDMI AUDIO platform driver to support HDMI
AUDIO codec driver's loadable build.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00230920-1 HDMI AUDIO: add support for HDMI audio module build
Chen Liangjun [Wed, 24 Oct 2012 04:31:59 +0000 (12:31 +0800)]
ENGR00230920-1 HDMI AUDIO: add support for HDMI audio module build

HDMI driver can be divided into 3 parts: machine driver, platform
driver, codec driver.To support HDMI AUDIO loadable module build, HDMI
machine driver should be built as loadable.

In this patch, adjust HDMI audio driver's struct: move HDMI audio platform
 driver to snd-soc-imx-objs(snd-soc-imx-objs would always be
build-in).In this case, user need only build HDMI AUDIO machine driver
as loadable.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00229938 pxp/v4l2: check return value of kmalloc against NULL
Robby Cai [Wed, 17 Oct 2012 01:01:35 +0000 (09:01 +0800)]
ENGR00229938 pxp/v4l2: check return value of kmalloc against NULL

This is needed sanity check, because on Ubuntu it's likely that low memory
will happen. This patch also makes this memory allocated from dma zone.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229665 pxp: correct crop setting
Robby Cai [Mon, 15 Oct 2012 13:36:44 +0000 (21:36 +0800)]
ENGR00229665 pxp: correct crop setting

The settings in the PXP_PS_BUF, PXP_OUT_PS_ULC, and PXP_OUT_PS_LRC will
determine the subset of the PS buffer, or clipped PS source buffer, that
will be used in the output buffer.

HW_PXP_OUT_PS_LRC should set the scaled output size rather than the origin
size when scaling.

Please refer to the "Clipping source images" section in RM for how it works.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00227965 EPDC: Init sequence leaves EDPC clocks on
Michael Minnick [Tue, 16 Oct 2012 23:07:20 +0000 (18:07 -0500)]
ENGR00227965 EPDC: Init sequence leaves EDPC clocks on

A small logic bug prevents the init sequence from properly turning
off the clocks. This leads to the clocks being always on
if the first update does not complete due to the screen being blanked.

Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
11 years agoENGR00229785 pgc: disable display power gating when FB_MXC_ELCDIF_FB configured
Robby Cai [Tue, 16 Oct 2012 07:53:29 +0000 (15:53 +0800)]
ENGR00229785 pgc: disable display power gating when FB_MXC_ELCDIF_FB configured

Only enable power gating for PXP and EPDC. The feature for ELCDIF still need to
be verified.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229803-2 sii902x: add dependency on CONFIG_FB_MXC_ELCDIF_FB
Robby Cai [Tue, 16 Oct 2012 08:21:28 +0000 (16:21 +0800)]
ENGR00229803-2 sii902x: add dependency on CONFIG_FB_MXC_ELCDIF_FB

Add dependency on CONFIG_FB_MXC_ELCDIF_FB, to avoid build error if as module.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229803-1 lcdif: export mxcfb_elcdif_register_mode needed by sii902x driver
Robby Cai [Tue, 16 Oct 2012 08:08:29 +0000 (16:08 +0800)]
ENGR00229803-1 lcdif: export mxcfb_elcdif_register_mode needed by sii902x driver

This is needed when build sii902x hdmi driver as module

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229473 elcdif fb: fix lcd framebuffer potential recursive locking
Robby Cai [Sun, 14 Oct 2012 13:33:21 +0000 (21:33 +0800)]
ENGR00229473 elcdif fb: fix lcd framebuffer potential recursive locking

This can be detected by enabling CONFIG_LOCKDEP and CONFIG_PROVE_LOCKING
The dump log:

=============================================
[ INFO: possible recursive locking detected ]
3.0.35-02140-gb4181ce-dirty #959
---------------------------------------------
swapper/1 is trying to acquire lock:
 ((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88

 but task is already holding lock:
  ((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88

  other info that might help us debug this:
   Possible unsafe locking scenario:

CPU0
----
 lock((fb_notifier_list).rwsem);
 lock((fb_notifier_list).rwsem);

*** DEADLOCK ***

May be due to missing lock nesting notation

5 locks held by swapper/1:
 #0:  (&__lockdep_no_validate__){+.+.+.}, at: [<8027f244>] __driver_attach+0x48/0x98
 #1:  (&__lockdep_no_validate__){+.+.+.}, at: [<8027f254>] __driver_attach+0x58/0x98
 #2:  (registration_lock){+.+.+.}, at: [<8023a17c>] register_framebuffer+0x18/0x24c
 #3:  (&fb_info->lock){+.+.+.}, at: [<80238dc8>] lock_fb_info+0x18/0x3c
 #4:  ((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88

stack backtrace:
[<800405c4>] (unwind_backtrace+0x0/0xf8) from [<80097c78>] (__lock_acquire+0x1644/0x1c18)
[<80097c78>] (__lock_acquire+0x1644/0x1c18) from [<80098748>] (lock_acquire+0x84/0x98)
[<80098748>] (lock_acquire+0x84/0x98) from [<804d0aa8>] (down_read+0x34/0x44)
[<804d0aa8>] (down_read+0x34/0x44) from [<80088758>] (__blocking_notifier_call_chain+0x44/0x88)
[<80088758>] (__blocking_notifier_call_chain+0x44/0x88) from [<800887b4>] (blocking_notifier_call_chain+0x18/0x20)
[<800887b4>] (blocking_notifier_call_chain+0x18/0x20) from [<802397e0>] (fb_set_var+0x264/0x290)
[<802397e0>] (fb_set_var+0x264/0x290) from [<8024a320>] (lcd_init_fb+0x54/0x70)
[<8024a320>] (lcd_init_fb+0x54/0x70) from [<8024a3f0>] (lcd_fb_event+0x44/0xb4)
[<8024a3f0>] (lcd_fb_event+0x44/0xb4) from [<80088514>] (notifier_call_chain.isra.1+0x74/0xd0)
[<80088514>] (notifier_call_chain.isra.1+0x74/0xd0) from [<80088774>] (__blocking_notifier_call_chain+0x60/0x88)
[<80088774>] (__blocking_notifier_call_chain+0x60/0x88) from [<800887b4>] (blocking_notifier_call_chain+0x18/0x20)
[<800887b4>] (blocking_notifier_call_chain+0x18/0x20) from [<8023a2d4>] (register_framebuffer+0x170/0x24c)
[<8023a2d4>] (register_framebuffer+0x170/0x24c) from [<8024fe8c>] (mxc_elcdif_fb_probe+0x464/0x564)
[<8024fe8c>] (mxc_elcdif_fb_probe+0x464/0x564) from [<8028031c>] (platform_drv_probe+0x18/0x1c)
[<8028031c>] (platform_drv_probe+0x18/0x1c) from [<8027f0f0>] (driver_probe_device+0x90/0x19c)
[<8027f0f0>] (driver_probe_device+0x90/0x19c) from [<8027f290>] (__driver_attach+0x94/0x98)
[<8027f290>] (__driver_attach+0x94/0x98) from [<8027e2e4>] (bus_for_each_dev+0x5c/0x88)
[<8027e2e4>] (bus_for_each_dev+0x5c/0x88) from [<8027eabc>] (bus_add_driver+0x188/0x250)
[<8027eabc>] (bus_add_driver+0x188/0x250) from [<8027f750>] (driver_register+0x78/0x13c)
[<8027f750>] (driver_register+0x78/0x13c) from [<8001c838>] (mxc_elcdif_fb_init+0x38/0x48)
[<8001c838>] (mxc_elcdif_fb_init+0x38/0x48) from [<80035334>] (do_one_initcall+0x34/0x178)
[<80035334>] (do_one_initcall+0x34/0x178) from [<80008968>] (kernel_init+0x84/0x124)
[<80008968>] (kernel_init+0x84/0x124) from [<8003b614>] (kernel_thread_exit+0x0/0x8)

In fact, we don't need support dynamically switch the framebuffer.
so, we only need do once registeration in probe function.

Signed-off-by: Robby Cai <R63905@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00227728 csi/v4l: add V4L2_CAP_VIDEO_CAPTURE & V4L2_CAP_STREAMING capability
Robby Cai [Fri, 12 Oct 2012 13:48:40 +0000 (21:48 +0800)]
ENGR00227728 csi/v4l: add V4L2_CAP_VIDEO_CAPTURE & V4L2_CAP_STREAMING capability

add V4L2_CAP_VIDEO_CAPTURE & V4L2_CAP_STREAMING capability for QUERYCAP ioctl.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00227873-2 mx6sl: enable pxp v4l2 option in defconfig
Robby Cai [Thu, 11 Oct 2012 07:10:13 +0000 (15:10 +0800)]
ENGR00227873-2 mx6sl: enable pxp v4l2 option in defconfig

Enable CONFIG_VIDEO_MXC_PXP_V4L2 option.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00227873-1 pxp/v4l2: make the v4l2 output device index auto assigned
Robby Cai [Wed, 10 Oct 2012 07:17:27 +0000 (15:17 +0800)]
ENGR00227873-1 pxp/v4l2: make the v4l2 output device index auto assigned

It used the hard-coded '0' for historical reason.
This patch changes it to -1 to make video device minor to
be automatically assigned.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00227726 csi: Disable csi clock when it's inactive
Robby Cai [Thu, 11 Oct 2012 06:50:34 +0000 (14:50 +0800)]
ENGR00227726 csi: Disable csi clock when it's inactive

Disable csi clock when inactive, otherwise this prevents system from
entering low power mode.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229222 mmc: esdhc: allow MMC and SDIO cards switched to 1.8V signalling
Robby Cai [Thu, 11 Oct 2012 11:43:49 +0000 (19:43 +0800)]
ENGR00229222 mmc: esdhc: allow MMC and SDIO cards switched to 1.8V signalling

The current driver only allows SD cards to run at 1.8V.
This patch allows MMC and SDIO cards to be switched to 1.8V signalling

Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00227890 ts: fix elan touch screen gets no response upon suspend/resume
Robby Cai [Thu, 11 Oct 2012 09:18:15 +0000 (17:18 +0800)]
ENGR00227890 ts: fix elan touch screen gets no response upon suspend/resume

To reproduce:
1. let system enter suspend mode
2. touch the screen
3. after the system resumes, touch screen does not respond again.

The cause:
The touch screen interrupt is triggered by falling edge. During suspend stage,
once the screen has ever been touched, then the interrupt line will be always
pulled low. Since elan ts chip is always powered on and the interrupt gets no
chance to be handled during suspend stage, the interrupt line can not recover
to high to detect a new one.

Workaround:
Read out the pending data to make the touch screen come back alive.

Signed-off-by: LiGang <b41990@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00229905-2: board-mx6q_sabreauto add i2c ad7280 device
Adrian Alonso [Thu, 27 Sep 2012 19:32:31 +0000 (14:32 -0500)]
ENGR00229905-2: board-mx6q_sabreauto add i2c ad7280 device

* Add ad7280 I2C device support

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Oscar Luna <r01160@freescale.com>
11 years agoENGR00229905-1: adv7280 mipi csi2 tvin decoder support
Adrian Alonso [Mon, 15 Oct 2012 20:28:05 +0000 (15:28 -0500)]
ENGR00229905-1: adv7280 mipi csi2 tvin decoder support

* Add ADV728x mipi csi2 tvin decoder support
* Perform a hardware reset via i2c command
* Load recommended initial config settings
* Kconfig selection options
* Makefile build rules

Signed-off-by: Oscar Luna <r01160@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00230377 Sabreauto: Add eCompass support
Alejandro Sierra [Fri, 19 Oct 2012 03:01:39 +0000 (22:01 -0500)]
ENGR00230377 Sabreauto: Add eCompass support

Add eCompass support on Sabreauto platform

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00229725 Sabreauto: Support NAND SPINOR NOR SD on same config
Alejandro Sierra [Mon, 15 Oct 2012 23:13:47 +0000 (18:13 -0500)]
ENGR00229725 Sabreauto: Support NAND SPINOR NOR SD on same config

Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00225520 SDMA:fix kernel dump occasionally during I2C stress test
Nicolin Chen [Tue, 16 Oct 2012 08:20:03 +0000 (16:20 +0800)]
ENGR00225520 SDMA:fix kernel dump occasionally during I2C stress test

 Stress test with I2C devices occasionally caused kernel dump and panic:
==========================dump=start==========================
v4l_capture_testapp    0  TINFO  :
  Color space conversion YUV420->RGB565X success!
v4l_capture_testapp    0  TINFO  :
  Color space conversion YUV420->RGB565X success!
clean up environment...VPU interrupt received.

Unable to handle kernel paging request at virtual address ffdf401a
pgd = ba2a4000
[ffdf401a] *pgd=4fe1a811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT SMP
Modules linked in: mxc_v4l2_capture ipu_still ipu_bg_overlay_sdc
 ipu_prp_enc ipu_fg_overlay_sdc ipu_csi_enc ov5642_camera
  camera_sensor_clock [last unloaded: ipu_csi_enc]
CPU: 0    Not tainted  (3.0.35-2039-g267e004 #1)
PC is at sdma_int_handler+0x144/0x1a4
LR is at sdma_int_handler+0x70/0x1a4
pc : [<802663f4>]    lr : [<80266320>]    psr: 60000193
sp : ba3e7ca8  ip : bfee2100  fp : 00000001
r10: 80a67200  r9 : 80acbcf0  r8 : 00000003
r7 : 00000001  r6 : 00000001  r5 : 00000002  r4 : bfee20e0
r3 : ffdf4000  r2 : 00010104  r1 : ffdf4018  r0 : bfee2104
Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c53c7d  Table: 4a2a404a  DAC: 00000015
Process mxc_vpu_test.ou (pid: 3277, stack limit = 0xba3e62f0)
Stack: (0xba3e7ca8 to 0xba3e8000)
7ca0:                   80038f40 bfee2000 002977e3 bf9cda80
 80a6724c 00000000
7cc0: 00000000 00000022 80acbcf0 80a67200 00000001 800a5cb8
 0000f08f 00000000
[<802663f4>] (sdma_int_handler+0x144/0x1a4)
 from [<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
[<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
 from [<800a5e24>] (handle_irq_event+0x3c/0x5c)
[<800a5e24>] (handle_irq_event+0x3c/0x5c)
 from [<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
[<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
 from [<800a5620>] (generic_handle_irq+0x28/0x3c)
[<800a5620>] (generic_handle_irq+0x28/0x3c)
 from [<80040830>] (handle_IRQ+0x4c/0xac)
[<80040830>] (handle_IRQ+0x4c/0xac)
 from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
 from [<800764f4>] (__do_softirq+0x4c/0x140)
[<800764f4>] (__do_softirq+0x4c/0x140)
 from [<80076a90>] (irq_exit+0x94/0x9c)
[<80076a90>] (irq_exit+0x94/0x9c)
 from [<8003a1b4>] (do_local_timer+0x70/0x90)
[<8003a1b4>] (do_local_timer+0x70/0x90)
 from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
Exception stack(0xba3e7de8 to 0xba3e7e30)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
 from [<80071a88>] (vprintk+0x328/0x4a8)
[<80071a88>] (vprintk+0x328/0x4a8)
 from [<804ddb28>] (printk+0x1c/0x2c)
[<804ddb28>] (printk+0x1c/0x2c)
 from [<80390de0>] (vpu_ioctl+0x2cc/0x864)
[<80390de0>] (vpu_ioctl+0x2cc/0x864)
 from [<800fc314>] (do_vfs_ioctl+0x80/0x54c)
[<800fc314>] (do_vfs_ioctl+0x80/0x54c)
 from [<800fc818>] (sys_ioctl+0x38/0x5c)
[<800fc818>] (sys_ioctl+0x38/0x5c)
 from [<8003ff80>] (ret_fast_syscall+0x0/0x30)
Code: e594101c e5943038 e0811081 e0831101 (e5d13002)
---[ end trace 82daf36a5a07d470 ]---
Kernel panic - not syncing: Fatal exception in interrupt
Rebooting in 60 seconds..
==========================dump=end==========================
 This kernel dump only happened after one period of stress-test's done.

 From the dump info above, we just located the issue happened in SDMA driver.
 Regularly, it'd not be any problem when sdma_int_handler()'s called. But after
tracing, we found that in those occasional times, the last one irq of a channel
hadn't been responded while sdma_free_chan_resources() was already done.
 sdma_free_chan_resources() should be called in the end of the procedure. Any
irq wouldn't occur after its resources're freed.
 But considering about stress test, the test scripts uses "kill" cmd to close
aplay, which means pcm_free() might be called before last buffer's transmission
was finished. Plus, many modules're working in the same time during the test.
So CPU0, the only core can handle irq, would be busy with irq-handlings, while
the other CPU cores(i.e. CPU1~3) might be idle and deal with free() much faster
than CPU0's irq-handling. Then kernel panic.

 Since we know, in some extreme circumstances, the irq would not be handled in
time, we can manually handle the irq ONLY IF we could still detect one irq to
the channel in the beginning of free(), right before its resources's gonna be
freed.
 This Patch added checking code in the beginning of sdma_free_chan_resources()
to detect when the channel's gonna be freed if there's still one irq pended.
If so, just handle the irq manually before we free it.
 Again, considering about sdma_int_handler() might be running at the same time,
and if it already cleared the value of reg but hadn't handled the irq yet, also
added code to pend free() until irq to the channel was handled.

Signed-off-by: Nicolin Chen <b42378@freescale.com>
11 years agoENGR00229902: mx6q sabreauto tvin use io_init callback function
Adrian Alonso [Fri, 5 Oct 2012 15:22:52 +0000 (10:22 -0500)]
ENGR00229902: mx6q sabreauto tvin use io_init callback function

* Adv7180 use tvin io_init callback to configure csi0/ipu
  mux settings mx6q_csi0_io_init.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00229952 mxc_v4l2_capture: csi ic mem uses hard coded initial DMA base addr
Sheng Nan [Wed, 17 Oct 2012 06:14:06 +0000 (14:14 +0800)]
ENGR00229952 mxc_v4l2_capture: csi ic mem uses hard coded initial DMA base addr

When setup csi ic mem on the fly channel, the capture output buffer is
initialized with hard coded dummy address 0xdeadbeaf

This also causes IPU warning when use this channel:
imx-ipuv3 imx-ipuv3.0: IDMAC20's EBA0 is not 8-byte aligned

- use the pre-allocated dummy_frame.vaddress instead of 0xdeadbeaf

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00229962 Capture: ov5642/ov5640: update sensor params even if s_parm failed
Sheng Nan [Wed, 17 Oct 2012 06:55:10 +0000 (14:55 +0800)]
ENGR00229962 Capture: ov5642/ov5640: update sensor params even if s_parm failed

ioctl_s_parm for ov5642 and ov5640, it didn't check if sensor changed mode
successfully.
So it updates the sensor parameters with new framerate and new mode even
if the sensor failed to change mode.

The original framerate and mode is useful for the exposure calculation.
It should keep consistent with sensor actual work mode.

- This patch checks the return value of function which changes sensor mode
  If it succeed, update sensor parameters.

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00229924 MX6SL-Fix MMDC FIFO reset code.
Ranjani Vaidyanathan [Tue, 16 Oct 2012 13:15:03 +0000 (08:15 -0500)]
ENGR00229924 MX6SL-Fix MMDC FIFO reset code.

Write to the MMDC registers when resetting the MMDC after the
DDR I/Os have been floated.

This fixes the bug introduced by the commit:
"2a2f65bd07ad0f947794c2e5f2f825121805d663
MX6SL-Reset MMDC read FIFO in low power IDLE"

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00229695 MX6x-Set RBC counters correctly in STOP mode.
Ranjani Vaidyanathan [Mon, 15 Oct 2012 10:36:02 +0000 (05:36 -0500)]
ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.

The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.

With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00229321 Integrate GPU 4.6.9p8 kernel part driver
Loren Huang [Fri, 12 Oct 2012 06:31:36 +0000 (14:31 +0800)]
ENGR00229321 Integrate GPU 4.6.9p8 kernel part driver

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00224964-4 mxc_v4l2_capture: change capture stream off sequence
Sheng Nan [Mon, 15 Oct 2012 12:01:32 +0000 (20:01 +0800)]
ENGR00224964-4 mxc_v4l2_capture: change capture stream off sequence

Change v4l2 capture stream off sequence.
Both CSI MEM and CSI IC MEM channel wait for idmac eof and
disable csi firstly.

The disable sequence is:
- wait for idmac channel EOF, disable csi
- disable idmac channel
- disable smfc (CSI-->MEM channel)

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00224964-3 IPU: Capture: add csi wait4eof support of CSI-IC channel
Sheng Nan [Mon, 15 Oct 2012 12:00:25 +0000 (20:00 +0800)]
ENGR00224964-3 IPU: Capture: add csi wait4eof support of CSI-IC channel

current _ipu_csi_wait4eof only support CSI-->MEM channel

- add support of CSI_PRP_ENC_MEM
- add support of CSI_PRP_VF_MEM

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00224964-2 IPU: Capture: change csi disable sequence
Sheng Nan [Mon, 15 Oct 2012 10:00:10 +0000 (18:00 +0800)]
ENGR00224964-2 IPU: Capture: change csi disable sequence

The recommended sequence for disable csi is,
disable csi as soon as we get IDMAC eof interrupt.

- add wait for eof when disable csi.
- don't wait for eof when disable CSI-->MEM channel.

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00224964-1 Capture: ov5642: 5M mode works at low frame rate
Sheng Nan [Mon, 15 Oct 2012 09:49:27 +0000 (17:49 +0800)]
ENGR00224964-1 Capture: ov5642: 5M mode works at low frame rate

current setting of 5M (QSXGA) mode, sensor works at 2.5fps.
the expected frame rate is 7.5fps.

- use new ov5642 QSXGA firmware get from ov
  change sensor PLL settings 0x3010/0x3012
  QSXGA frame rate changes from 2.5 -- 7.5fps
- change mode between QSXGA@15fps and VGA@15fps go through quick change path.
  modify QSXGA_VGA quick change firmware due to the QSXGA PLL setting changes.
  keep value of 0x3010/0x3012 the same as VGA@15fps original value.

Signed-off-by: Sheng Nan <b38800@freescale.com>
11 years agoENGR00229708 [MX6SL] Fix all build warnings.
Nancy Chen [Mon, 15 Oct 2012 15:52:08 +0000 (10:52 -0500)]
ENGR00229708 [MX6SL] Fix all build warnings.

Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
11 years agoENGR00229630 vpu: need to manage pu regulator in suspend/resume
Anson Huang [Mon, 15 Oct 2012 23:01:17 +0000 (19:01 -0400)]
ENGR00229630 vpu: need to manage pu regulator in suspend/resume

If VPU is working before suspend, we need to disable its regulator
to make sure regulator can be off before suspend, then enable
its regulator before resume to work, we check vpu's open_count
to determine whether to disable/enable its regulator.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00229291 EPDC: MX6: Treat fully-collided VOID update as a collision
Michael Minnick [Fri, 12 Oct 2012 18:52:36 +0000 (13:52 -0500)]
ENGR00229291 EPDC: MX6: Treat fully-collided VOID update as a collision

The EPDC set the UPD_VOID (i.e. cancelled) bit in two cases:
1. No pixels needed updating
2. All pixels collided (COL bit also set)
The driver was miss-handling case 2. This fix causes case 2
to be treated as a collision and the update to be resubmitted.

Signed-off-by: Michael Minnick <michael.minnick@freescale.com>