ENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration.
In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
1. Disable on-chip pull-up, pull-down, and keeper
2. Disable hysteresis
3. Speed = 100 MHz
4. Slew rate = fast
The optimizition make the bias point match the optimum point, which
can maximize design margin.
Michael Minnick [Tue, 6 Nov 2012 19:21:50 +0000 (13:21 -0600)]
ENGR00232660 EPDC: Wrong panel loaded at boot
The wrong EPDC panel can be loaded at boot time if the machine
board file has multiple panel entries with the same video mode
parameter values. To reproduce, select a particular panel with
u-boot kernel command line parameters, for example:
video=mxcepdcfb:XYZZY
Add panel XYZZY to arch/arm/mach-mx6/board-mx6sl_evk.c after
an existing entry. Use the same video mode parameter settings
as the existing entry. On boot, the existing panel will be loaded
instead of the XYZZY panel because it comes earlier in the list
and happens to have the same video mode parameter values.
Solution: If the video mode parameter settings specified in
the call to msc_epdc_fb_set_par() match those of the panel
already loaded by mxc_epdc_fb_probe(), don't execute a
search for a new matching panel.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Sandor Yu [Thu, 8 Nov 2012 08:24:10 +0000 (16:24 +0800)]
ENGR00232930 Added default video mode check, make sure it is a CEA mode.
When system bootup without HDMI plugin, the default modelist
and default video mode will create.
Match default video mode in default CEA modelist, make sure
default video mode is a CEA mode.
Ryan QIAN [Fri, 26 Oct 2012 02:13:34 +0000 (10:13 +0800)]
ENGR00231273-02 mmc: sdhci: fix failed to call platform exit on removal
Since sdhci_pltfm_data is stored in platform_device_id, but in
sdhci_pltfm_remove, it tried to get sdhci_pltfm_data directly from
pdev->dev.platform_data. It will result that it could not get the correct
sdhci_pltfm_data, so that platform exit will not be called on sdhci module's
removal.
Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
make shi [Tue, 6 Nov 2012 07:52:24 +0000 (15:52 +0800)]
ENGR00232583 Mx6 USB host: Set HCD_FLAG_HW_ACCESSIBLE flag after clock gate
There is a USB hang issue when do system suspend/resume test with a USB
device plug in. The issue is caused by USB host driver accessing register
when clock is off. Currently set HCD_FLAG_HW_ACCESSIBLE bit before open
clock in ehci_fsl_bus_resume, it cause accessing register without clock.
So we should change the code call order to avoid driver access register
without clock.
- Set HCD_FLAG_HW_ACCESSIBLE software flag after HW clock turn on
- remove some unnecessary code in ehci_fsl_pre_irq
Anson Huang [Tue, 6 Nov 2012 22:47:26 +0000 (17:47 -0500)]
ENGR00232586 mx6: increase PUPSCR to make sure LDO is ready for resume
Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Adrian Alonso [Thu, 25 Oct 2012 20:15:26 +0000 (15:15 -0500)]
ENGR00231266-3: adv7280_mipi_tvin add regulator support
* Add regulator support
Set regulator voltage and enable them
On remove callback disable regulators
* Add callbacks for target platform custom
reset, power up/down and io pads configuration
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Wed, 24 Oct 2012 16:37:11 +0000 (11:37 -0500)]
ENGR00231266-2: adv7280_mipi_tvin add i2c dummy client for csi config
* Add i2c dummy client for csi-tx register map config
* adv7280 csi-tx reg banks are mapped in a different
memory map and respond to a different i2c slave address
that user can configure
* Add default config helper function
* Override slave csi-tx address if user provides a different
value.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Chen Liangjun [Wed, 31 Oct 2012 09:27:23 +0000 (17:27 +0800)]
ENGR00231773-8 ASRC: prevent user app from processing input/output processing
To finish a buffer convert in ASRC, user should 1. prepare input buffer,
2. prepare output buffer 3. wait for output buffer's completion 4.wait
for input buffer's comletion. The flow make user application ugly.
In this patch, pack steps above to 1 stop: ASRC_CONVERT.
When SDMA is use for periphal data transfer, dma request is trigger by
FIFO level. If the SDMA is started after the start of periphal, SDMA
would miss the first pulse and be not able to trigger itself.
In this patch, add interface to trigger a dma request manully.
Chen Liangjun [Wed, 31 Oct 2012 03:11:26 +0000 (11:11 +0800)]
ENGR00231773-5 ASRC: use poll mode to receive last period of ASRC data
ASRC driver use DMA to transfer data from ASRC output FIFO to memory.
However, DMA way require the data number in ASRC output FIFO being larger
than watermark level. Thus a dma request can trigger a DMA burst. For
the last period of output data, its number is possiblely less than output
FIFO watermark level. In this case, the output DMA would pending for the
last period of output data until timeout.
In this patch:
1 divide expected output data length into 2 parts: DMA part
and poll part. Using DMA to get the DMA part data and poll mode to
get the poll part.
2 to prevent user from processing these 2 parts above, kernel
buffers would be untouchable. User application only need send its data
buffer address to driver instead of query the kernel buffer.
Chen Liangjun [Fri, 26 Oct 2012 09:43:30 +0000 (17:43 +0800)]
ENGR00231773-4 ASRC: use scatter list and stall bit for asrc convert
In the origin code, ASRC driver use cyclic way to process DMA task
transfering data to/from ASRC input/output FIFO. In this case, it is
necessary that user application should promise that the input buffer
flow is continuous. If not, there would be 0 data be inserted into data
flow. The output data would be noisy.
In this patch,
1 use scatter list instead of cyclic SDMA: with scatter list,
SDMA would stop when the applied scatter list nents are finished.
2 set stall bit for ASRC "memory->ASRC->memory" convert to stop
ASRC convert when input data is not send into ASRC input FIFO in time.
Chen Liangjun [Fri, 26 Oct 2012 07:10:09 +0000 (15:10 +0800)]
ENGR00231773-3 ASRC: use kzalloc to allocate buffer to support scatterlist
For ASRC's "memory -> ASRC -> memory" using, new driver would support
model below: user input one buffer into ASRC and an corresponding output
buffer would be poped out. There is no timing requirement between this
input buffer and next input buffer. Thus driver would not use the cyclic
way to config SDMA and scatterlist is used. buffer allocated by
dma_alloc_coherent() can't support scatterlist well.
In this patch, use kzalloc to allocate buffer to support scatterlist.
Chen Liangjun [Fri, 26 Oct 2012 05:42:35 +0000 (13:42 +0800)]
ENGR00231773-2 ASRC: add work struct for asrc output data receive
SDMA driver can't promise receive all output data generated. Cause when
the data in output FIFO is less than ASRC output FIFO watermark, there
would be no DMA request generated and thus no SDMA transfer would
happens.
In this patch, add work struct to support ASRC driver receive last part
of data in OUTPUT FIFO in polling way.
Chen Liangjun [Fri, 26 Oct 2012 08:07:41 +0000 (16:07 +0800)]
ENGR00231773-1 ASRC: remove queue operation in ASRC driver
According to ASRC memory->ASRC->memory requirement, driver should
satisfy the feature below: user application would passed into one buffer
and waiting until the output buffer is generated. In this case, only one
buffer is on processing and it is no necessary to use the queue to do
the convert. What is worse, queue operation would make the ASRC driver
hard to understand and maintain.
In this patch, remove the queue operation in ASRC driver.
IPG_PERCLK is the parent of I2C. I2C needs a minimum of
12.8MHz as its input clock to achieve 400KHz speed. Hence
change the IPG_PERCLK speed accordingly.
MX6DQ/MX6DL - Set IPG_PERCLK at 22MHz (sourced from IPG_CLK)
MX6SL - Set IPG_PERCLK to 24MHz(Sourced from 24MHz XTAL).
Israel Perez [Wed, 31 Oct 2012 22:13:36 +0000 (17:13 -0500)]
ENGR00225875-2 i.MX6Q/Solo Sabreauto Bluetooth H4 fix uart rx timeouts.
Bluetooth H4 protocol is very susceptible to data reception timeouts.
DMA transfer only happen when ICD or AGTIM interrutps are trigger.
ICD only happen when a N idle frames are present on rx line
and rx FIFO is empty.
Meanwhile Aging timer is trigger when data in FIFO was been sitting for a
period of 8 frames.
This patch enable both in order to dispatch data as fast is possible only
when the select uart have enable DMA flag.
Signed-off-by: Israel Perez <B37753@freescale.com>
Israel Perez [Wed, 31 Oct 2012 22:06:44 +0000 (17:06 -0500)]
ENGR00225875-1 i.MX6Q/Solo SabreAuto Infineon Bluetooth uart3 config
Configure MUX settings for bluetooth operation over UART3.
Enable RTS,CTS and DMA only for uart3.
Affected files :
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabreauto.h
arch/arm/mach-mx6/board-mx6solo_sabreauto.h
arch/arm/plat-mxc/include/mach/iomux-mx6q.h
On behalf of Francisco Munoz <francisco.munoz@freescale.com>.
Some modification are needed also on hciattach tool.
Signed-off-by: Israel Perez <B37753@freescale.com>
Robby Cai [Fri, 2 Nov 2012 07:58:40 +0000 (15:58 +0800)]
ENGR00232000: Fix "dmaengine: failed to get dma1chan0: (-22)" when boot
The log from [MX6DL/S_SD]:
...
mxc_sdc_fb mxc_sdc_fb.1: register mxc display driver ldb
dmaengine: failed to get dma1chan0: (-22)
dmaengine: failed to get dma1chan1: (-22)
dmaengine: failed to get dma1chan2: (-22)
dmaengine: failed to get dma1chan3: (-22)
dmaengine: failed to get dma1chan4: (-22)
dmaengine: failed to get dma1chan5: (-22)
dmaengine: failed to get dma1chan6: (-22)
dmaengine: failed to get dma1chan7: (-22)
dmaengine: failed to get dma1chan8: (-22)
dmaengine: failed to get dma1chan9: (-22)
dmaengine: failed to get dma1chan10: (-22)
dmaengine: failed to get dma1chan11: (-22)
dmaengine: failed to get dma1chan12: (-22)
dmaengine: failed to get dma1chan13: (-22)
dmaengine: failed to get dma1chan14: (-22)
dmaengine: failed to get dma1chan15: (-22)
...
It happens when there are many DMA-engine drivers in the system and
dmaengine_get() is called. dmaengine_get() will call dma_chan_get(), which will
call device_alloc_chan_resources() literally on channels of available dma
drivers unless reach -ENODEV. device_alloc_chan_resources() is implemented
in the individual dma drivers, which could return -EINVAL rather than -ENODEV,
then the above messages print out (doesn't hurt, however).
Indeed, the dmaengine_get() and dmaengine_put() is not needed and thus removed.
Lionel Xu [Wed, 31 Oct 2012 08:40:37 +0000 (16:40 +0800)]
ENGR00231778 MX6 ESAI: Adjust channel support capability of cpu/codec dai
To adjust the channel support capability, codec dai does not support mono
playback and record, while esai dai does, thus making the whole audio
codec only support stereo and above channel playback/record.
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Hongzhang Yang [Thu, 1 Nov 2012 11:26:44 +0000 (19:26 +0800)]
ENGR00232087-1 MX6: Enable PU LDO gating.
1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
for a big nand chip Micron MT29F64G08AFAAAWP(8GB), we got the following wrong
result:
.............................................
"mtd: partition size too small (0)"
.............................................
We can not get any partition.
The "4g(test)" partition triggers a overflow of the "size". The memparse()
returns 4g to the "size", but the size is "unsigned long" type, so a overflow
occurs, the "size" becomes zero in the end.
This patch changes the "size"/"offset" to "unsigned long long" type,
and replaces the UINT_MAX with ULLONG_MAX for macros SIZE_REMAINING and
OFFSET_CONTINUOUS.
Tony LIU [Thu, 1 Nov 2012 02:15:18 +0000 (10:15 +0800)]
ENGR00231965 MX6 USB CV 3.0 test fail
- For USB CV 3.0 test, the gap between the ACK of set_address and
the subsequent setup packet may be very little, say 500us, and
if the latency we handle the ep completion is greater than this
gap, there is no response to the subsequent packet. It will
cause CV test fail
- There is another way to set the address, it should set the bit 24
to 1 with the right address, and then IC controller will set the
address when the IN req complete instead of SW do it. It is more
fast so it can fix the CV 3.0 test fail issue
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Matthieu CASTET [Mon, 19 Mar 2012 14:35:25 +0000 (15:35 +0100)]
mtd: support ONFI multi lun NAND
With onfi a flash is organized into one or more logical units (LUNs).
A" logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Robin Gong [Wed, 31 Oct 2012 13:41:16 +0000 (21:41 +0800)]
ENGR00231910 PU regulator: do not disable PU regulator
If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP. Signed-off-by: Robin Gong <b38343@freescale.com>
Alejandro Sierra [Wed, 24 Oct 2012 20:32:37 +0000 (15:32 -0500)]
ENGR00231063 Sabreauto: fix share pins SD Card and NFC
SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 21:43:41 +0000 (14:43 -0700)]
ENGR00230538-5: CAAM: Add SM register defs
Add SM register defs, and expanded driver-private storage.
These add changes to the driver private areas for the CAAM
controller and CAAM Secure Memory subsystems, and expand register
definitions to include the Secure Memory subsystems as reflected
in multiple areas (controller, rings, secure memory itself).
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 20:27:24 +0000 (13:27 -0700)]
ENGR00230538-2: CAAM: Add Secure Memory and SNVS properties
Add Secure Memory and SNVS properties to MX6 configuration.
Previous configurations of MX6 platform device definition lacked
specific propeties for CAAM Secure Memory and SNVS. Added these
properties to define register ranges for both entities.
Also corrected the name for the offset of the address range for
CAAM Secure Memory to more accurately reflect it's purpose.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 20:18:37 +0000 (13:18 -0700)]
ENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection
3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock
IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Robin Gong [Fri, 26 Oct 2012 11:19:43 +0000 (19:19 +0800)]
ENGR00230981-3 pfuze: add suspend voltage set interface
Implement set_suspend_voltage for buck switch of PF100, and set_suspend_enable
/set_suspend_disable interface for LDO(VGENx). Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Wed, 24 Oct 2012 10:28:59 +0000 (18:28 +0800)]
ENGR00230981-2 pfuze:standby voltage increase for PFM
There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd Signed-off-by: Robin Gong <b38343@freescale.com>
Huang Shijie [Fri, 26 Oct 2012 08:04:03 +0000 (16:04 +0800)]
ENGR00231331 mtd: gpmi: add kernel command line to enable gpmi in arm2 board
In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.
make shi [Thu, 18 Oct 2012 07:59:18 +0000 (15:59 +0800)]
ENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO
The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Wayne Zou [Wed, 24 Oct 2012 01:36:00 +0000 (09:36 +0800)]
ENGR00230910 IPU: wrong display to downsize large resolution frame on split mode
Fix bug: IPU IC resize ratio overflow when downsizing large resolution frame
using split mode, for example downsize 4080x2720 frame into 1920x1080 frame.
Otherwise, the downsized frame is wrong.
Chen Liangjun [Wed, 24 Oct 2012 04:31:59 +0000 (12:31 +0800)]
ENGR00230920-1 HDMI AUDIO: add support for HDMI audio module build
HDMI driver can be divided into 3 parts: machine driver, platform
driver, codec driver.To support HDMI AUDIO loadable module build, HDMI
machine driver should be built as loadable.
In this patch, adjust HDMI audio driver's struct: move HDMI audio platform
driver to snd-soc-imx-objs(snd-soc-imx-objs would always be
build-in).In this case, user need only build HDMI AUDIO machine driver
as loadable.
Robby Cai [Mon, 15 Oct 2012 13:36:44 +0000 (21:36 +0800)]
ENGR00229665 pxp: correct crop setting
The settings in the PXP_PS_BUF, PXP_OUT_PS_ULC, and PXP_OUT_PS_LRC will
determine the subset of the PS buffer, or clipped PS source buffer, that
will be used in the output buffer.
HW_PXP_OUT_PS_LRC should set the scaled output size rather than the origin
size when scaling.
Please refer to the "Clipping source images" section in RM for how it works.
Michael Minnick [Tue, 16 Oct 2012 23:07:20 +0000 (18:07 -0500)]
ENGR00227965 EPDC: Init sequence leaves EDPC clocks on
A small logic bug prevents the init sequence from properly turning
off the clocks. This leads to the clocks being always on
if the first update does not complete due to the screen being blanked.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Robby Cai [Thu, 11 Oct 2012 09:18:15 +0000 (17:18 +0800)]
ENGR00227890 ts: fix elan touch screen gets no response upon suspend/resume
To reproduce:
1. let system enter suspend mode
2. touch the screen
3. after the system resumes, touch screen does not respond again.
The cause:
The touch screen interrupt is triggered by falling edge. During suspend stage,
once the screen has ever been touched, then the interrupt line will be always
pulled low. Since elan ts chip is always powered on and the interrupt gets no
chance to be handled during suspend stage, the interrupt line can not recover
to high to detect a new one.
Workaround:
Read out the pending data to make the touch screen come back alive.
Signed-off-by: LiGang <b41990@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
Alejandro Sierra [Mon, 15 Oct 2012 23:13:47 +0000 (18:13 -0500)]
ENGR00229725 Sabreauto: Support NAND SPINOR NOR SD on same config
Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Nicolin Chen [Tue, 16 Oct 2012 08:20:03 +0000 (16:20 +0800)]
ENGR00225520 SDMA:fix kernel dump occasionally during I2C stress test
Stress test with I2C devices occasionally caused kernel dump and panic:
==========================dump=start==========================
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
clean up environment...VPU interrupt received.
Unable to handle kernel paging request at virtual address ffdf401a
pgd = ba2a4000
[ffdf401a] *pgd=4fe1a811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT SMP
Modules linked in: mxc_v4l2_capture ipu_still ipu_bg_overlay_sdc
ipu_prp_enc ipu_fg_overlay_sdc ipu_csi_enc ov5642_camera
camera_sensor_clock [last unloaded: ipu_csi_enc]
CPU: 0 Not tainted (3.0.35-2039-g267e004 #1)
PC is at sdma_int_handler+0x144/0x1a4
LR is at sdma_int_handler+0x70/0x1a4
pc : [<802663f4>] lr : [<80266320>] psr: 60000193
sp : ba3e7ca8 ip : bfee2100 fp : 00000001
r10: 80a67200 r9 : 80acbcf0 r8 : 00000003
r7 : 00000001 r6 : 00000001 r5 : 00000002 r4 : bfee20e0
r3 : ffdf4000 r2 : 00010104 r1 : ffdf4018 r0 : bfee2104
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 4a2a404a DAC: 00000015
Process mxc_vpu_test.ou (pid: 3277, stack limit = 0xba3e62f0)
Stack: (0xba3e7ca8 to 0xba3e8000)
7ca0: 80038f40bfee2000002977e3bf9cda80 80a6724c00000000
7cc0: 000000000000002280acbcf080a6720000000001800a5cb8 0000f08f00000000
[<802663f4>] (sdma_int_handler+0x144/0x1a4)
from [<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
[<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
from [<800a5e24>] (handle_irq_event+0x3c/0x5c)
[<800a5e24>] (handle_irq_event+0x3c/0x5c)
from [<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
[<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
from [<800a5620>] (generic_handle_irq+0x28/0x3c)
[<800a5620>] (generic_handle_irq+0x28/0x3c)
from [<80040830>] (handle_IRQ+0x4c/0xac)
[<80040830>] (handle_IRQ+0x4c/0xac)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<800764f4>] (__do_softirq+0x4c/0x140)
[<800764f4>] (__do_softirq+0x4c/0x140)
from [<80076a90>] (irq_exit+0x94/0x9c)
[<80076a90>] (irq_exit+0x94/0x9c)
from [<8003a1b4>] (do_local_timer+0x70/0x90)
[<8003a1b4>] (do_local_timer+0x70/0x90)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
Exception stack(0xba3e7de8 to 0xba3e7e30)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<80071a88>] (vprintk+0x328/0x4a8)
[<80071a88>] (vprintk+0x328/0x4a8)
from [<804ddb28>] (printk+0x1c/0x2c)
[<804ddb28>] (printk+0x1c/0x2c)
from [<80390de0>] (vpu_ioctl+0x2cc/0x864)
[<80390de0>] (vpu_ioctl+0x2cc/0x864)
from [<800fc314>] (do_vfs_ioctl+0x80/0x54c)
[<800fc314>] (do_vfs_ioctl+0x80/0x54c)
from [<800fc818>] (sys_ioctl+0x38/0x5c)
[<800fc818>] (sys_ioctl+0x38/0x5c)
from [<8003ff80>] (ret_fast_syscall+0x0/0x30)
Code: e594101ce5943038e0811081e0831101 (e5d13002)
---[ end trace 82daf36a5a07d470 ]---
Kernel panic - not syncing: Fatal exception in interrupt
Rebooting in 60 seconds..
==========================dump=end==========================
This kernel dump only happened after one period of stress-test's done.
From the dump info above, we just located the issue happened in SDMA driver.
Regularly, it'd not be any problem when sdma_int_handler()'s called. But after
tracing, we found that in those occasional times, the last one irq of a channel
hadn't been responded while sdma_free_chan_resources() was already done.
sdma_free_chan_resources() should be called in the end of the procedure. Any
irq wouldn't occur after its resources're freed.
But considering about stress test, the test scripts uses "kill" cmd to close
aplay, which means pcm_free() might be called before last buffer's transmission
was finished. Plus, many modules're working in the same time during the test.
So CPU0, the only core can handle irq, would be busy with irq-handlings, while
the other CPU cores(i.e. CPU1~3) might be idle and deal with free() much faster
than CPU0's irq-handling. Then kernel panic.
Since we know, in some extreme circumstances, the irq would not be handled in
time, we can manually handle the irq ONLY IF we could still detect one irq to
the channel in the beginning of free(), right before its resources's gonna be
freed.
This Patch added checking code in the beginning of sdma_free_chan_resources()
to detect when the channel's gonna be freed if there's still one irq pended.
If so, just handle the irq manually before we free it.
Again, considering about sdma_int_handler() might be running at the same time,
and if it already cleared the value of reg but hadn't handled the irq yet, also
added code to pend free() until irq to the channel was handled.
Sheng Nan [Wed, 17 Oct 2012 06:55:10 +0000 (14:55 +0800)]
ENGR00229962 Capture: ov5642/ov5640: update sensor params even if s_parm failed
ioctl_s_parm for ov5642 and ov5640, it didn't check if sensor changed mode
successfully.
So it updates the sensor parameters with new framerate and new mode even
if the sensor failed to change mode.
The original framerate and mode is useful for the exposure calculation.
It should keep consistent with sensor actual work mode.
- This patch checks the return value of function which changes sensor mode
If it succeed, update sensor parameters.
ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.
The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Sheng Nan [Mon, 15 Oct 2012 09:49:27 +0000 (17:49 +0800)]
ENGR00224964-1 Capture: ov5642: 5M mode works at low frame rate
current setting of 5M (QSXGA) mode, sensor works at 2.5fps.
the expected frame rate is 7.5fps.
- use new ov5642 QSXGA firmware get from ov
change sensor PLL settings 0x3010/0x3012
QSXGA frame rate changes from 2.5 -- 7.5fps
- change mode between QSXGA@15fps and VGA@15fps go through quick change path.
modify QSXGA_VGA quick change firmware due to the QSXGA PLL setting changes.
keep value of 0x3010/0x3012 the same as VGA@15fps original value.
Anson Huang [Mon, 15 Oct 2012 23:01:17 +0000 (19:01 -0400)]
ENGR00229630 vpu: need to manage pu regulator in suspend/resume
If VPU is working before suspend, we need to disable its regulator
to make sure regulator can be off before suspend, then enable
its regulator before resume to work, we check vpu's open_count
to determine whether to disable/enable its regulator.
Michael Minnick [Fri, 12 Oct 2012 18:52:36 +0000 (13:52 -0500)]
ENGR00229291 EPDC: MX6: Treat fully-collided VOID update as a collision
The EPDC set the UPD_VOID (i.e. cancelled) bit in two cases:
1. No pixels needed updating
2. All pixels collided (COL bit also set)
The driver was miss-handling case 2. This fix causes case 2
to be treated as a collision and the update to be resubmitted.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE
MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Jack Lee [Wed, 3 Oct 2012 05:31:47 +0000 (13:31 +0800)]
ENGR00223348 EPDC: Unable to enable DISPLAY regulator
In the maxim 17135 driver, the power good is confirmed by the
power good GPIO polarity change when comparing the status at
the beginning of driver probe and display regulator enabled.
However, it is not reliable since the initial value of the GPIO
is not constant. Normally, it is 1 but it can be 0 after system reset
unexpectedly. Now, it is changed to POK bit checking in FAULT register.
ENGR00229470-2 MX6SL-Add support for debug UART to be sourced from 24MHz.
If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
ENGR00229470-1 MX6SL-Add support for debug UART to be sourced from 24MHz.
If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Sheng Nan [Sat, 13 Oct 2012 06:33:13 +0000 (14:33 +0800)]
ENGR00211376 Capture: ov5640_mipi: the QVGA is brighter
change ov5640_init_mode sequence according to ov's suggestion
ov5640 support two method of size switching, scaling and subsampling
exposure calculation when change size between scaling and subsampling
- scaling: image size bigger than 1280*960
- subsampling: image size smaller than 1280*960
This patch changes the sequence of ov5640_init_mode()
1. setting mipi csi2 (no change).
2. check mode
- if it is in INIT_MODE, go throught initial procedure
- if sensor changes between scaling and subsampling,
go through exposure calcualtion
- otherwise, configure mode directly.
3. other procedures keep the same.
ENGR00229464 MX6SL-Update the SOC voltages based on datasheet
Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
projects / karo-tx-linux.git / log