Jason Chen [Fri, 15 Apr 2011 08:25:57 +0000 (16:25 +0800)]
ENGR00141363 ARM imx53 clock: change di0 clock default parent to pll3
If enable both LVDS and one display device use external di clock, there will
be conflict between their clock parent -- both use pll4 on mx53. So it need
change di0 clock parent to pll3, and then uart parent need change to pll2 to
avoid console mess.
Jason Chen [Wed, 23 Feb 2011 10:18:50 +0000 (18:18 +0800)]
ENGR00139635 mxc edid: add edid name sysnode
Add name sysnode to mxc_ddc and sii902x, which can be check under:
/sys/devices/platform/mxc_ddc.0/fb_name
or
/sys/devices/platform/sii902x.0/fb_name
It's the name of fb fix id which it associated.
Tony Lin [Tue, 11 Jan 2011 10:01:03 +0000 (18:01 +0800)]
ENGR00137979-1 add performance monitor driver
add performance monitor driver.
sample:
cd /sys/devices/platform/mxs-perfmon.0/
'echo 1 > MIDn-xxx' to enable monitor this channel
n: channel number; xxx: name of channel (PXP, LCD...)
you can enable the multiple channels you want to
monitor respectively using this command.
use following command to check the channel is enabled
'cat MIDn-xxx'
1: enable; 0: disable
'echo read > Monitor' to monitor all read activities
'echo start > Monitor' to start monitoring
'echo fetch > Monitor' to get a snapshot of monitor statistics.
'cat xxx_Count' to show the statistics.
xxx: name of statistics, (Data, Transfer, Latency...)
'echo clear > Monitor' to clear snapshot of monitor statistics.
'echo stop > Monitor' to stop monitoring
- Removed setting of pfd_disable_mask bits in pfd enable/disable functions.
This feature, which automates the disabling of the APLL, was being used
incorrectly and is less clear than manually enabling/disabling PFD and
APLL clocks directly.
- Added wait for APLL relocking after APLL is enabled.
Peter Chen [Tue, 22 Mar 2011 09:27:17 +0000 (17:27 +0800)]
ENGR00140950 mfg: fix the bug that ubiformat utility breaks utp protocol
ubiformat includes command, data, command periods,
it breaks utp protocol for PUT commands. So we add two operations to fix it.
One is sending busy to host before the data periods begins.
The second is adding a new command to waiting ubiformat's command period.
Signed-off-by: Li Xingyu <b02754@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Jason Liu [Tue, 12 Apr 2011 06:24:00 +0000 (14:24 +0800)]
ENGR00141977 MX50: Kernel can't boot up
Kernel can't boot up on 2.6.38 branch due to the that
Russell has made one change to MT_HIGH_VECTORS, which
result in this memory region is read-only, so, memcpy
will fail when copy suspend code into iram.
Since the iram code region need excuting and rw attribue,
change the MT_HIGH_VECTORS to MT_MEMORY.
ENGR00122019 SAHARA: Add padding around buffers to prevent cache incoherency
Added padding of 64 bytes (cache line size for Cortex-A8) around
buffers that are used by the hardware to prevent any cache
coherency problems that could arise if buffers share a cache line
with some other data that is used by the CPU.
ENGR00141478-2 SAHARA: Move header file to include directory
The user mode libsahara library relied on header file
drivers/mxc/security/sahara2/include/sahara.h. However, to make
the lib build after headers_install step and to remove dependency on
kernel source, moved this header to include/linux/mxc_sahara.h.
These changes are specific to the include/linux folder.
ENGR00141478-1 SAHARA: Move header file to include directory
The user mode libsahara library relied on header file
drivers/mxc/security/sahara2/include/sahara.h. However, to make
the lib build after headers_install step and to remove dependency on
kernel source, moved this header to include/linux/mxc_sahara.h.
These are the necessary changes in the SAHARA driver to use the new
header file in the new location.
Liu Ying [Tue, 8 Mar 2011 06:59:21 +0000 (14:59 +0800)]
ENGR00140391 ISL29023:Keep int thresholds in interrupt handler
We used to set the interrupt thresholds to the measure range
of the light sensor in the interrupt handler, this potentially
makes user poll on the input event and never be waken up.
This patch keeps the interrupt thresholds in the interrupt
handler and is tested on MX53 SMD.
Liu Ying [Tue, 22 Feb 2011 09:11:30 +0000 (17:11 +0800)]
ENGR00139383-2 Add ISL29023 light sensor support
This patch adds ISL29023 light sensor support.
Users may control the light sensor work at
different modes/ranges/resolutions or read
the lux value via sysfs.
A power state node is also created in sysfs.
If the light sensor works at ALS once mode,
users need to power down/power up the sensor
before read the lux value again.
Currently, IR(Infra Red) mode is not supported.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
ENGR00141647 AUDIO,SGTL5000: Fix codec error after reset
sgtl5000 codec not work after board reset, this is caused by
sgtl5000 using register address step is 2, and snd-soc-core can't
handle this as we expect, so we have to fill the register cache by
reading register out when initialization instead of providing a default
value array.
Huang Shijie [Mon, 30 Aug 2010 01:51:18 +0000 (09:51 +0800)]
ENGR00141399-5 OCOTP: add the ocotp driver
Add a new driver for On-Chip OTP controller. The driver
will register all the register names of all the banks to /sys/.
You can use the following commands to manipulate the OTP banks:
Richard Zhao [Tue, 22 Mar 2011 02:22:15 +0000 (10:22 +0800)]
ENGR00141399-2 iMX5x: add clock debug information
Expose clock debug information to debugfs, which makes it easier for clock
system debug by using tools like powerdebug developed by Linaro power
management group.
For long term, this can go into common clock framework, but so far it depends
on the process of common clk API development. Once the common clk API is
ready in upstream, the clock debug information will be based on it too.
The implementation based on common clk API had also been finished and
reviewed with Jeremy.
ARM: iMX5x: fix clock debug enable_count error
Signed-off-by: Yong Shen <yong.shen@linaro.org> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com>
Frank Li [Tue, 29 Mar 2011 01:45:35 +0000 (09:45 +0800)]
ENGR00141217-8 ASoC: SGTL5000: Add DAP support for sgtl5000 codec
upgrade to 2.6.38 kernel
Add Digital Audio Process(DAP) for sgtl5000 codec
Audio: imx53,loco,audio: make Loco sgtl5000 codec work
config audmux when ssi probed, and fix sdma watermark settings
Jason Chen [Wed, 23 Feb 2011 09:31:54 +0000 (17:31 +0800)]
ENGR00141217-5 IPU\VPU\GPU: upgrade to 2.6.38
Add drivers/mxc
Add drivers/video/mxc
Add drivers/media/mxc
fb device: change acquire_console_sem to console_lock
And release_console_sem to console_unlock
Add DMA Zone support
Add TVE driver, add regulator
Add hdmi support
Add VPU
Frank Li [Tue, 22 Feb 2011 09:34:58 +0000 (17:34 +0800)]
ENGR00141217-3 MX53 MSL part upgrade to 2.6.38
imx51_babbage:
imx53_smd: add i2c device
imx53_smd: add i2c board device info
imx53_smd: add esdhc device support
imx53_smd: Add SRTC devices
imx53_smd: enable the AHCI SATA
imx53_smd: Add GPIO Keypad support
imx53_ard: enable ARD board bootup
imx53_ard: add ethernet pin mux
imx53_ard: add smsc911x device
imx53_loco: add i2c device
imx53_loco: change sii902x i2c device
imx53_loco: register v4l2 output device
imx53_loco: add srtc device
imx53_loco: enable the AHCI SATA
imx53_loco: Add GPIO Keypad support
imx53_evk: add evk and arm2 boards io setting and set up display
imx5: add ipu\vpu
imx5: clock.c: remove RATE_PROPAGATES
imx5: Add clock, dvfs, busfreq, sdram_autogating support.
imx5: fix warnings on boot
imx5: add v4l2 device
imx5: add board_is_rev support
imx5: Add sdma support for i.Mx53 and i.Mx51
imx5: add p1003
imx5: add ipuv3
imx5: add sata
imx5: add pmic board files
imx5: add pm function
imx5: add iram config
imx5: add gpu
imx5: fix clock debug enable_count error
imx53: add gpio irq support for mx53
imx53: change PWM backlight device register method to dynamic
imx53: change v4l2 device register method to dynamic
imx53: add vpu devices support
imx53: add dvfs-core and busfreq devices register method
imx53: Add usb devices
imx53: add i2c pad settings
imx53: add ssi support
Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com> Signed-off-by: Zhang Yan <b34916@freescale.com>
Zhang Jiejing [Mon, 22 Nov 2010 09:14:32 +0000 (17:14 +0800)]
ENGR00133978 PM: add time sensitive debug function to suspend & resume
There was some driver is slow on suspend/resume,
but some embeded system like eReader,Cellphone
are time sensitive,this commit will report the slow
driver on suspend/resume, the default value is 500us(0.5ms)
Also, the threshold can be change by modify
'/sys/power/device_suspend_time_threshold' to change the threshold,
it is in microsecond.
The output is like:
PM: device platform:soc-audio.2 suspend too slow, takes 606.696 msecs
PM: device platform:mxc_sdc_fb.1 suspend too slow, takes 7.708 msecs
the default state of suspend driver is default off,
if you want to debug the suspend time, echo time in
microsecond(u Second) to /sys/powe/device_suspend_time_threshold
eg: I want to know which driver suspend & resume takes
more that 0.5 ms (500 us), you can just :
Richard Zhao [Wed, 21 Apr 2010 04:46:59 +0000 (12:46 +0800)]
ENGR00122691-1 Add atheros driver ath6kl
Integrate atheros driver package from atheros company.
It's mainly for AR6003.
NGR00132491-1 ath6kl upgrade: change Kconfig
This series of patches are for upgrading Atheros AR6003(ath6kl)
in 31 kernel to 35 kernel.
The WLAN_80211 config option has been changed to WLAN in 35 kernel.
Some i.MX parts (MX31, MX37) need to have usb host queue descriptors
and/or buffers in on-chip IRAM in cases of heavily loaded memory
system (i.e. large LCDs).
Enable partial low interrupt latency mode for ARM1136
Enable partial low interrupt latency mode for ARM1136
This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.