ENGR00218013-5 HDMI: Add SDMA to help HDMI audio support multi buffer
For chip version easily than TO1.1, HDMI use internel DMA enginue for
audio tranfer. Due to capability of HDMI module, FIFO underrun is
unavoidable.
For chip TO 1.2, introducing SDMA to help HDMI audio DMA. With the help
of SDMA, HDMI audio can use ping-pong buffer mechanism and FIFO underrun
can be avoid.
In this path: Add SDMA support for i.MX6Q later than TO1.2.
ENGR00218013-4 MX6Q ARM2: Set HDMI event as event 2 of SDMA event
Select external SDMA request as SDMA event 2 for MX6Q ARM2 board.
SDMA event 2 can be configured HDMI or IPU. Signed-off-by: Chen Liangjun <b36089@freescale.com>
ENGR00218624 ASRC: set dma_data to 0 before config SDMA
To allocate an SDMA channel, imx_dma_data struct is need. However,
if the member dma_request_p2p is not set to 0 before configuration,
SDMA driver would treat the channel as p2p(periphal to periphal) DMA and
set SDMA channel context in p2p way. In the worst case, SDMA would
access some unexisted address cause of mis configuration above and thus
cause kernel panic or hang.
In this patch, set imx_dma_data struct to 0 once it is allocated from
stack.
Robin Gong [Thu, 26 Jul 2012 09:00:48 +0000 (17:00 +0800)]
ENGR00172083 SPI-NOR mx6: fix failed erase uboot ENV on SPI-NOR by MFG tool
In MFG tool will use "flash_eraseall /dev/mtd0" command to erase whole mtd0
partition, but u-boot environment params are stored in offset 0xc0000 which
exceed the u-boot patition 0x40000, it means the "flash_eraseall" command only
erase u-boot partition, but not environment area. So we need increase the size
of u-boot partition to 0x100000 as what we remain 1MB for u-boot. Signed-off-by: Robin Gong <B38343@freescale.com>
make shi [Wed, 25 Jul 2012 02:10:45 +0000 (10:10 +0800)]
ENGR00215520-03 Mx6:USB host: USB Host1 modulization
- remove mx6_usb_h1_init() in board specific initialization files
- Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c
to support the usb_h1 modulization
- Export necessary function which is used in usb_h1.c
make shi [Fri, 20 Jul 2012 02:43:09 +0000 (10:43 +0800)]
ENGR00215520-01 Mx6:USB host: USB Host1 modulization
- Add USB_EHCI_ARC_H1 configuration to imx6_defconfig and imx6s_defconfig,
the default configuration is selected as "y"
- add related USB_EHCI_ARC_H1 configuration to Makefile
- add related USB_EHCI_ARC_H1 configuration to Kconfig
* wifi downlink throughput is tested by iperf in open air.
** writing performance for SDMA is much slower than ADMA, it might
be an issue which needs further investigation.
ENGR00216848 MX6 DL dual display failed on HDMI and LVDS
HDMI output video mode is 1080p, LVDS output is XGA.
The IPU bandwidth is not enough to support the two display output
when IPU HSP clock setting to 200MHz,
increase the IPU HSP clock to 270MHz and dual display can work.
When system not boot up all cores, such as adding max_cpus=n,
n<NR_CPUS, then the conservative governor will increase the cpu
frequncy to the highest freq and never get to down.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
Liu Ying [Tue, 24 Jul 2012 10:01:35 +0000 (18:01 +0800)]
ENGR00182061-3 MX6 SabreSD:Correct camera pwdn function
This patch adds 2ms sleep after camera power down signal
is set to high or to low to ensure power down or up
is successful. OV5640/OV5642 camera specs say that they
require this condtion to be true - for PWDN to go low,
power must first become stable(DVDD to PWDN>=1ms), so
this patch simply use 2ms which should be enough.
Rong Dian [Tue, 24 Jul 2012 02:34:15 +0000 (10:34 +0800)]
ENGR00218070 imx6 battery: fix charger led first wrong indication status
because boot time gap between led framwork and battery driver init,when system
boots with charger attatched, charger led framwork loses the first charger
online event,add once extra power_supply_changed can fix this issure
Robin Gong [Tue, 24 Jul 2012 01:56:28 +0000 (09:56 +0800)]
ENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by default
To validate LDO bypass function fully, enable CONFIG_MX6_INTER_LDO_BYPASS
on u-boot and kernel, only for mx6sl. Signed-off-by: Robin Gong <b38343@freescale.com>
Yuxi Sun [Tue, 17 Jul 2012 09:24:51 +0000 (17:24 +0800)]
ENGR00182271-3 V4L2 OVERLAY: Add IPU2 overaly support for fore ground
When vf_rotation > IPU_ROTATE_VERT_FLIP, canncel the MEM_ROT_VF_MEM
- MEM_FG_SYNC channel link and using IPU_IRQ_PRP_VF_ROT_OUT_EOF irq
to trigger double buffer switch.
When vf_rotation <= IPU_ROTATE_VERT_FLIP,cannel the CSI_PRP_VF_MEM
- MEM_FG_SYNC channel link, and using IPU_IRQ_PRP_VF_OUT_EOF to
trigger double buffer switch.
Alejandro Sierra [Fri, 20 Jul 2012 18:51:41 +0000 (13:51 -0500)]
ENGR00217857: Changed iomux ID pin
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID
This fix was already implemented on CR ENGR00180424. Somehow this
was not included on newer releases.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Tony LIU [Fri, 20 Jul 2012 09:54:35 +0000 (17:54 +0800)]
ENGR00217721-5 usb gadget random transfer fail
usb driver part
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Tony LIU [Fri, 20 Jul 2012 01:51:17 +0000 (09:51 +0800)]
ENGR00217719 usb gadget msc may enumeration fail if msc storage response slow
- communication between the usb driver and msc class driver is using
raise_exception/handle_excpetion, such mechaism can only have two
events(exceptions) at most, one is on processing and another is store to be
executed after the current one completed.
If the first one processing is very slow, and the third one occur, then the
second one will be overwriten by the third one and then the second event is
lost and then enumeration failed
- since it is the linux community code, it is hard to change the whole frame
work, currently only a work around is provided
- because this issue is brought in when the first reset event, when this
event occur, a lun sync will happen and it will cost much time, but in fact
this lun sync is not necessary for the first reset event, the work around
is to skip this lun sync.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Tony LIU [Fri, 20 Jul 2012 01:28:27 +0000 (09:28 +0800)]
ENGR00217716 mfgtool host frequently reset bus during transfer
- the response in csw to request sense will be 1 due to UTP change
some storage information
- host will reset the bus if response to request sense is 1
- change the response to 0 if CONFIG_FSL_UTP is defined
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
We must prevent module unloading if some devices are still attached to
l2tp_eth driver.
Signed-off-by: Eric Dumazet <edumazet@google.com> Reported-by: Denys Fedoryshchenko <denys@visp.net.lb> Tested-by: Denys Fedoryshchenko <denys@visp.net.lb> Cc: James Chapman <jchapman@katalix.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
We need to validate the number of pages consumed by data_len, otherwise frags
array could be overflowed by userspace. So this patch validate data_len and
return -EMSGSIZE when data_len may occupies more frags than MAX_SKB_FRAGS.
Signed-off-by: Jason Wang <jasowang@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time. This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends. Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[add irq_enter()/irq_exit() in do_local_timer] Signed-off-by: UCHINO Satoshi <satoshi.uchino@toshiba.co.jp> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The statically defined I/O memory regions for the i.MX21 on chip
peripherals and the on board I/O peripherals of the i.MX21ADS board
overlap. This results in a kernel crash during startup. This is fixed
by reducing the memory range for the on board I/O peripherals to the
actually required range.
Steve Cornelius [Wed, 11 Jul 2012 21:48:09 +0000 (14:48 -0700)]
ENGR00215945-3: caam: Improve error recovery on failed RNG4 kickstart
RNG4 requires a kickstart process to transition into running mode.
In the case that this kickstart process errors, the driver is shut
back down (under the assumption that internal random padding of keys
or data cannot occur).
In an isolated case, the kickstart failed to start the RNG, an error
was returned, and the driver attempted to de-register an RNG function
that never completed, causing a crash. (This is difficult to test for
without manual intervention).
Therefore, amended the driver shutdown process to only de-register
the hardware RNG when an instance kickstarted without error.
This does NOT correct the kickstart problem, only the consequences.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Sat, 7 Jul 2012 00:35:55 +0000 (17:35 -0700)]
ENGR00215945-2: Fix directions in cache coherence functions
During a bug search, a review turned up two places where the wrong
direction was used in dma_sync function calls. In practice. these
compiled away to be inconsequential on the platform in question, but
this may not be true on all platforms.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Thu, 5 Jul 2012 23:41:29 +0000 (16:41 -0700)]
ENGR00215945-1: Rework scatterlist handling for bi-endian platforms
Former versions of this (ARM) branch of this driver reworked the hardware-
readable scatter/gather list to operate as a set of 32-bit integers,
rather than a packed structure of smaller sizes, which cannot burst-read
correctly on a little-endian platform.
Integration of caamhash.c revealed subtle ways in which the ordering of
items written to a hardware s/g list could create bugs, such as the
"final" bit being written to an entry that would later be updated with
a size, inadvertently erasing the bit (e.g. such as sg_to_sec4_sg_last()
before sg_to_sec4_sg()).
Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended descriptor
structs + hardware scatterlists to use kzalloc() instead of kmalloc(), so
as to ensure that residue data would not be ORed in with the correct data.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
ENGR00217621-02 - SPDC : fix build error enable both SPDC and EPDC
- Add early param to select SPDC module, which can enable SPDC and
EPDC modules build in kernel. Fix the build error because they both
modules use the same gobal varaible.
ENGR00217621-01 - MSL : Add early param to select SPDC
- Add "spdc" in uboot command line to select SPDC module for
AUO panel display. By default, EPDC is enabled and SPDC is
disabled, which are mutually exclusive because they share
the same data line.
Fugang Duan [Thu, 28 Jun 2012 07:29:43 +0000 (15:29 +0800)]
ENGR00215202 - MSL : Ethernet phy LAN8720 cable link issue
- Phy LAN8720 link status is un-stable when disable clock from clock
enabled status. The phy register_1[link status] bit is pulsatile,
so driver will print:
PHY: 1:00 - Link is Up - 100/Full
PHY: 1:00 - Link is Down
PHY: 1:00 - Link is Up - 100/Full
PHY: 1:00 - Link is Down
...
- Because phy clock source is from FEC internel clock, if disbale clock
from enabled status, some LAN8720 phys status machine is in disorder
and cannot display link status correctly. So, it need to do phy hw
reset before clock enable.
this patch is adding a ioctl for vpu to check the phy addr before vpu
start using this addr, this use case is common in some Direct Render case,
the VPU 's framebuffer phy memory is allocate by GPU, if the address given
by GPU have some wrong, like pass a virtual address, vpu will hang the system.
Add this IOCTL to be the goalkeeper, this IOCTL can check whether the phy
address was virtual memory or the address is within phy memory of your DDR.
The phy memory valild check is now doing best effort:
1. check whether is was allocated by vmalloc(), which must be a phy un-continus
2. check whether is was beyound DDR's top address, usually the other driver
pass a virtual address as a phy address.
ENGR00216013-2 mx6: not call memblock_free after reserve memory.
Remove call memblock_free after reserve memory with memblock_allocate().
The function of memblock_free is to remove the memory block from reserve list
of memblock, it will totally lost the info about how much phy memory
we have.
Skipping call this can make the reserved memory be accountable in
memblock With no side-effect.
After doing this, we can know how much our phy memory is, then can add check
in our driver like(vpu) to check the phy memory valid or not before vpu start
use the address.
add a function to check the end address including reserved memory,
this API can provide the top address of phy memory,
it can be used to check if the phy memory is valild in some driver
like VPU.
Ryan QIAN [Mon, 25 Jun 2012 23:39:36 +0000 (07:39 +0800)]
ENGR00217120 mmc: esdhc: implement std tuning for fsl sdhc ip
1. in mx6sl, it adds sd3.0 uhs mode capability indicator bits.
2. in mx6sl, exe_tune and smp_clk_sel bits for standard tuning procedure
have been put in ACMD12_ERR reg
Ryan QIAN [Wed, 11 Jul 2012 00:50:12 +0000 (08:50 +0800)]
ENGR00216961: MMC/SDIO: gate off sdio clk when MMC_POWER_OFF is set
1. For sdio card, only when MMC_POWER_OFF is set,
sdhci_disable_clk will be called for sdio. otherwise sdio clk
will not be gated.
2. Set MMC_CAP_POWER_OFF_CARD caps in esdhc, so that
sdio_bus power off and clock gate off card through
to pm_runtime interface.
Gary Zhang [Wed, 11 Jul 2012 02:15:42 +0000 (10:15 +0800)]
ENGR00209905 WM8962: support for continuously playback diff sample bit streams
support for continuously playback different sample bit audio
streams with -Dplughw:0,0 option
such as the command: 'aplay -Dplughw:0,0 16bit.wav 24bit.wav'
before prohibit reenter hw_params, now remove this limitation
to support this feature.
ENGR00217018 [Mx6 ]Need to set 1.1V as PU default voltage
1. Need to set 1.1V as default PU value, as when first time VPU
or GPU try to enable PU regulator, it will use this default
value as PU voltage setting.
2. For DL, as its default setpoint is set to middle point,
we need to add a usecount for 400M PFD, because when system
enter 24M, it will disable 400M PFD if its previous setpoint
is middle, if not add this usecount when we init the bus freq
setpoint, then the usecount will be wrong when first time system
enter 24M bus mode.
Rong Dian [Thu, 12 Jul 2012 03:20:17 +0000 (11:20 +0800)]
ENGR00216946: battery: increase update period to 2 minutes
increase update period to 2 minutes. Due to improper hardware design,
when enable HDCP function, the I2C2 bus pins function is change to DDC
function,the CPU loading is high when I2C failed transfer data via I2C
bus,so decrease battery update voltage frequency.
Israel Perez [Mon, 9 Jul 2012 16:59:23 +0000 (11:59 -0500)]
ENGR00172077 [MX6Q_ARD]TVIN: Kernel dump and Error Messages
adv7180.c code was not working properly in this new release because some
changes done in mxc_v4l_capture.c driver.
Also mostly of the error messages and kernel dump problem which were related
to csi_enc are already fixed on this release.
In order to fix on previous releases csi and ipuv3 fixes
should be applied or back ported.
Signed-off-by: Israel Perez <B37753@freescale.com>
ENGR00216031 [MX6]Need to force bus freq to highest point when suspend
1. When bus freq is at 400M setpoint, currently bus freq will not
set to high setpoint when suspend, but some drivers which need
high bus freq enable clock before bus freq resume, so the request
of high bus freq will be ignore until next high bus freq device is
enabled,it will result in some devices need high bus freq but bus freq
dirver stay at med setpoint. So we need to force bus freq to
highest setpoint before suspend to avoid such scenario.
2. Clean up PU LDO turn on/off, move to regulator driver and maintain by
VPU and GPU driver.
projects / karo-tx-linux.git / log