- Add NAPI methods.
NAPI can improve the performance of high-speed networking,
which can reduce the cpu loading of interrupt generate and
drop packets.
- Enet RX FIFO overruns number has been reduced by NAPI method.
For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.
Terry Lv [Mon, 16 Apr 2012 09:44:12 +0000 (17:44 +0800)]
ENGR00179722: MLB: set correct mlb sys clock in mx6dl
In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.
ENGR00172292 usb otg: enable dtds postpone free on mx6
We found this bug occurs again on mx6 when running
CTS with ADB over USB. The system will hang without
any log, and screen a little mess.
It's proved to be a known USB IP issue: USB controller
may access a wrong address for the dTD and then hang.
Re enable this workaround to avoid any system unstability.
Jason Liu [Tue, 17 Apr 2012 11:08:00 +0000 (19:08 +0800)]
ENGR00179851: i.mx6dl: map the MEM mode to STANDBY mode
Due to i.mx6dl TO1.0(TKT094231), Suspend/resume cannot work
stable under deep sleep mode(Dormant, MEM MODE) thus we need
map the MEM mode to STANBY mode(ARM will not power off), this
issue will be fixed on TO1.1
Jason Liu [Tue, 17 Apr 2012 10:53:53 +0000 (18:53 +0800)]
ENGR00179782: i.mx6: consolidate mx6q/dl_revision() support
The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
Liu Ying [Mon, 16 Apr 2012 04:40:37 +0000 (12:40 +0800)]
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.
ENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.
The current SDMA use the new DMA tranfer direction. But the UART still
uses the old. This cause the RX failed.
So use the new DMA transfer direction for UART.
Tony LIU [Mon, 16 Apr 2012 07:47:23 +0000 (15:47 +0800)]
ENGR00179679 Fix usb gadget suspend issue connected to usb charger
- the root cause of this issue is during resume process, USB clock
is not turned on for this USB charger case so that the second
suspend is processed without USB clock, it cause system hang
- in udc resume process, at this situation, we should exit low
power mode to enable the b session valid intrrupt to close the
usb clock when detach from usb charger
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Liu Ying [Fri, 13 Apr 2012 10:10:14 +0000 (18:10 +0800)]
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
This patch includes some of the clk enable/disable changes from rev2
Check the version of the HDMI IP to determine whether the fifo
threshold needs to be high. The i.Mx6dl version of the HDMI doesn't
need the workaround. All other parts of the workaround are used
for both parts for code simplicity.
----------------------------------------------------------
For i.Mxq, set the Threshold of audio fifo as: FIFO depth - 2 (fixed
and independent of the number of channels actually used).
Use unspecified length ahb bursts (using fixed INCRx will make the
audio dma fail).
Additionally and in order to get it working on all conditions it will
be necessary to run the following sw steps at startup of video and audio
(or when video changes or audio changes):
1-Configure AUD_N1 and AUD_CTS1 registers with final value and let the
AUD_N2, AUD_N3, AUD_CTS2 and AUD_CTS3 to 0s.
2-Configure start and end addresses of audio DMA registers.
3-Start DMA operation
4-Configure the AUD_CTS2 and AUD_CTS3 with the final value.
5-Configure the AUD_N2 and AUD_N3 with final value.
ENGR00179574: MX6- Add bus frequency scaling support
Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.
To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Wayne Zou [Fri, 13 Apr 2012 00:28:06 +0000 (08:28 +0800)]
ENGR00179513-3 V4L2: Add VDOA tiled format support
Support for VDOA tiled format IPU_PIX_FMT_TILED_NV12 up to 1080p progressive
streams, and IPU_PIX_FMT_TILED_NV12F tiled format up to xga interlaced streams
currently.
b07117 [Wed, 21 Dec 2011 13:32:02 +0000 (21:32 +0800)]
ENGR00170747 gpu driver : add AXI BUS ERROR message
AXI BUS ERROR may occur in very low possibility,
this debug message exist before 4.4.2, but removed in 4.6.x,
need add it back to trace critical gpu issue
Wayne Zou [Fri, 13 Apr 2012 06:16:21 +0000 (14:16 +0800)]
ENGR00179631 MX6 SabreSD: Add MIPI DSI Display support
Add MIPI DSI Display support on mx6 SabreSD board.
MIPI DSI needs pll3_pfd_540M clock source for 540MHz.
if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz.
So add command line option disable_ldb when using MIPI DSI display.
ENGR00179642 Remove a workaround for suspend/resume
Remove a workaround for suspend/resume:
The workaround is turn on clock before gpu entering suspend.
After clock code bug is fixed, this workaround becomes no necessary.
Allen Xu [Tue, 10 Apr 2012 09:02:36 +0000 (17:02 +0800)]
ENGR00179284-4 support ONFI NAND device on mx6q_arm2_pop board
if the NAND chip supports ONFI feature and the board supports ONFI
DDR transfer mode, users could enable ONFI DDR transfer by add command
line parameter "onfi_support"
Robin Gong [Thu, 12 Apr 2012 06:40:42 +0000 (14:40 +0800)]
ENGR00179497-1 ECSPI: disable ecspi clock after probe and spi transfer
before, it enable spi clock after probe, never been disable unless driver
removed. To reduce power, disable clock after probe, and enable it before
every spi transfer and disable it after spi transfer Signed-off-by: Robin Gong <B38343@freescale.com>
Adrian Alonso [Mon, 9 Apr 2012 17:16:53 +0000 (12:16 -0500)]
ENGR00179226: imx-esai remove tx personal reset during record
* Remove transmitter personal reset during stream record
this could potencially block concurrent play/record support.
* Remove receiver personal reset calls, rx is always
operational.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Jason Liu [Wed, 11 Apr 2012 09:16:36 +0000 (17:16 +0800)]
ENGR00179426-1 i.mx6: iomux: NO_PAD_I/NO_PAD_MUX not defined
NO_PAD_I/NO_PAD_MUX not defined, which will cause build error
According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0
for the pins which does not have PAD/MUX config.
Larry Li [Tue, 10 Apr 2012 09:12:51 +0000 (17:12 +0800)]
ENGR00178597 [MX6DL/S] Multi-instance test in GC880 cause system hang
In our code 3d sharder clock uses 3d core clock CCGR field as its
enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock
as 2d core clock, while disable 2d core clock, it will disable 3d
core by mistake.
To fix it, remove the enable bit setting of 3d shader clock in
clock.c file.
ENGR00179129 Board support for I2C AMFM module for IMX6Q and IMX6DL
Modifications in ARD board file to support the Audio for AMFM
module for IMX6Q and IMX6DL (REV A and REV B) Supported for
kernel 3.0.15. Also it contains the I2C configuration for
the AMFM module.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
ENGR00179178 [RTC]Enable both wakealarm and common power wakeup
For RTC driver, as not all RTCs support alarm and wakeup, so the
framework only support alarm or wakeup, not both of them, as our
rtc can support alarm and wakeup function, to simplify the unit
test interface for power off and wakeup, we add both wakealarm and
common power wakeup sysfs interface to our RTC driver.
Chen Liangjun [Wed, 28 Mar 2012 05:36:18 +0000 (13:36 +0800)]
ENGR00178612 ESAI:add support for esai call asrc
ESAI can call ASRC for sample rate convert if the input sample rate
is not support.
1 ESAI will decide whether to use ASRC for sample rate convert in
imx-cs42888.c. If ASRC is need, the asrc_enable will be set.
2 In imx-pcm-dma-mx2.c, according to the value of asrc_enable, the
dma driver would decide whether to alloc another p2p dma channel to
support MEMORY-->ASRC_INPUT-->ASRC_OUTPUT-->ESAI_TX_FIFO route.
3 The code support 2 channel,24/32 bit audio file playback.
The issue is hard to reproduce in normal envrionment. And
the reproduce rate is about 40% when doing VTE auto test.
while the driver did report being busy when the link is down
or no transmission buffers are available, it did not stop the
queue, causing instant retries. furthermore, transmission being
triggered with link down was caused by unconditional queue
wakes, especially on timeouts.
Now, wake queue only if link is up and transmission buffers
are available, and dont forget to wake queue when link has
been adjusted. next, add stop queue notification upon driver
induced transmission problems, so network stack has a chance
to handle the situation.
Chen Liangjun [Sat, 31 Mar 2012 06:25:23 +0000 (14:25 +0800)]
ENGR00177235-2 SDMA: add p2p dma mode
Add code to support p2p dma mode.Add membership in imx_dma_data
struct to support P2P dma script. Because the P2P dma script
need 2 dma request to trigger DMA burst.
Chen Liangjun [Tue, 20 Mar 2012 05:18:25 +0000 (13:18 +0800)]
ENGR00177235-1 SDMA: add p2p dma mode
Add support for p2p(peripheral to peripheral) dma mode in SDMA
module.
1 Add p2p script membership in struct sdma_channel to support
device to device tranfer.
2 P2P dma script need more configure information then memory to
peripheral or peripheral to memory script. we configure these
information into watermark_level.
Dave Martin [Thu, 23 Jun 2011 16:10:05 +0000 (17:10 +0100)]
ARM: assembler.h: Add string declaration macro
Declaring strings in assembler source involves a certain amount of
tedious boilerplate code in order to annotate the resulting symbol
correctly.
Encapsulating this boilerplate in a macro should help to avoid some
duplication and the occasional mistake.
Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Adrian Alonso [Tue, 3 Apr 2012 21:01:23 +0000 (16:01 -0500)]
ENGR00178915: imx6 clock fix build warnings
* Fix build warnings
* clock.c: In function '_clk_pll1_enable':
warning: no return statement in function returning non-void
* clock.c: In function 'mx6_clocks_init':
warning: unused variable 'reg'
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Hui Wang [Wed, 24 Aug 2011 09:41:47 +0000 (17:41 +0800)]
serial/imx: support to handle break character
The imx UART hardware controller can identify BREAK character and the
imx_set_termios() can accept BRKINT set by users, but current existing
imx_rxint() can't pass BREAK character and TTY_BREAK to the tty layer
as other serial drivers do (8250.c omap_serial.c).
Here add code to handle BREAK character and pass it to tty layer.
To detect error occurrence, i use URXD_ERR to replace (URXD_OVRRUN |
URXD_FRMERR | ...) because any kind of error occurs, URXD_ERR will
always be set to 1.
I put the URXD_BRK to the first place to check since when BREAK error
occurs, not only URXD_BRK is set to 1, but also URXD_PRERR and
URXD_FRMERR are all set to 1. This arrangement can filter out fake
parity and frame errors when BREAK error occurs.
Signed-off-by: Hui Wang <jason77.wang@gmail.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
(cherry picked from commit 019dc9ea8d528eb3640bbba604e1e5a2f6994b1f)
make shi [Thu, 5 Apr 2012 05:09:18 +0000 (13:09 +0800)]
ENGR00178932 USB: fix two USB otg common bug for i.MX6
- Built in gadget device driver, plug in USB cable with no response,
the reason is USB VBUS wakeup is not enable after OTG switch,make
sure pdata->port_enables is 1 even if the pdata is otg device pdata.
-Without modprobe or built in gadget device driver,after plug out
the USB otg cable,will output "wait otg vbus change timeout!".The
reason is we get error otgsc data after USB enter low power mode.
ENGR00160472 - MX6: add Ethernet ANSI/IEEE 802.2 LLC support in defconfig.
- Add Ethernet ANSI/IEEE 802.2 LLC support. And the packet with
IP head "ETH_P_802_2" will be processed in Ethernet stack L3 layer.
- If disable the feature, ethernet stack will drop the LLC packets.
1. When system not boot up all cores, interactive governor
will not work;
2. Adjust the default timer_rate to 50ms instead of 20ms to
avoid too many freq up/down change.
TO1.0 parts donot boot properly after the following commit: 88d3af87222b37e454acd6a8de3b0cf18180da32
MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq
is below 400MHz.
Correct gpt_clk was not getting enabled. Fix by adding the
appropriate gpt_clk.
Uart 3 and NFC pins are shared.
Uart 3 enablement is done by passing an early parameter
called "uart3" from uboot. Both interfaces (Uart3 and NFC)
can NOT coexist on the same configuration at the same time.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Robin Gong [Sun, 1 Apr 2012 04:38:22 +0000 (12:38 +0800)]
ENGR00178629 i.MX6 sabresd:support software power off by SNVS setting
On sabresd board, PMIC_ON_REQ control pmic power on/off, we can set TOP and
DP_EN of SNVS_LPCR to implement power off by software. On this way,SNVS RTC
alarm can work after power off. The description of register can be found on
other SNVS block document which provided by IC team, not i.MX6 RM.
projects / karo-tx-linux.git / log