Stephen Warren [Wed, 25 Mar 2015 02:07:34 +0000 (20:07 -0600)]
ARM: bcm2835: implement phys_to_bus/bus_to_phys
The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a
VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally
access DRAM via this same L2 cache (although they always bypass the L1
cache). Peripherals select whether to use or bypass the cache via the
top two bits of the bus address.
An IOMMU exists between the ARM CPU and the rest of the system. This
controls whether the ARM CPU's accesses use or bypass the L1 and/or L2
cache. This IOMMU is configured/controlled exclusively by the VideoCore
CPU.
In order for DRAM accesses made by the ARM core to be coherent with
accesses made by other DMA peripherals, we must program a bus address
into those peripherals that causes the peripheral's accesses to use the
same set of caches that the ARM core's accesses will use.
On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of
the L2 cache. This corresponds to addresses based at 0x40000000.
On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of
the L2 cache. This corresponds to addresses based at 0xc0000000.
This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according
to those rules.
For full details of this setup, please see Dom Cobley's description at:
http://lists.denx.de/pipermail/u-boot/2015-March/208201.html
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038
https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Wed, 25 Mar 2015 02:07:33 +0000 (20:07 -0600)]
Create API to map between CPU physical and bus addresses
On some SoCs, DMA-capable peripherals see a different address space to
the CPU's physical address space. Create an API to allow platform-agnostic
drivers to convert between the two address spaces when programming DMA
operations.
This API will exist on all platforms, but will have a dummy implementation
when this feature is not required. Other platforms will enable
CONFIG_PHYS_TO_BUS and provide the required implementation.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Tue, 24 Mar 2015 05:01:01 +0000 (23:01 -0600)]
usb: dwc2: fix bulk transfers
When I created wait_for_chhltd(), I noticed that some instances of the
code it replaced expected the ACK bit to be set and others didn't. I
assumed this was an accidental inconsistency in the code, so wrote
wait_for_chhltd() to always expect ACK to be set. This code appeared to
work correctly for both enumeration of USB keyboards and operation of
USB Ethernet devices. However, this change broke USB Mass Storage (at
least my USB SD card reader). This change reverts to exactly the
original behaviour. I'm not sure why the ACK bit isn't always set
(perhaps a quirk in the USB HW or DWC2 controller), but the code works
this way!
Fixes: 5be4ca7d6ac8 ("usb: dwc2: unify waiting for transfer completion") Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 17:08:14 +0000 (11:08 -0600)]
usb: dwc2: remove restriction on buffer length
Each USB transfer is split up into chunks that are held in an aligned
buffer. This imposes a limit on the size of each chunk, but no limit on
the total size of transferred data. Fix the logic in chunk_msg() not to
reject large transfers, but simply take the size of the aligned buffer
into account when calculating the chunk size.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 17:08:13 +0000 (11:08 -0600)]
usb: dwc2: fix aligned buffer usage
The original aligned_buffer usage:
a) Uselessly copied data into the aligned buffer even for IN
transactions. Fix this my making the copy conditional.
b) Always programmed the HW to transfer to/from the start of the aligned
buffer. This worked fine for OUT transactions since the memcpy copied
the OUT data to this location too. However, for large IN transactions,
since the copy from the aligned buffer to the "client" buffer was
deferred until after all chunks were transferred. it resulted in each
chunk's transfer over-writing the data for the first transfer. Fix
this by copying IN data as soon as it's received.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 05:48:54 +0000 (22:48 -0700)]
usb: dwc2: remove control_data_toggle[]
The control data toggle resets to DATA1 at the start of the data phase
of every setup transaction. We don't need a global variable to store
the value; we can just store it on the stack.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 05:48:52 +0000 (22:48 -0700)]
usb: dwc2: refactor submit_bulk_msg to be common
Move the body of submit_bulk_msg() into new function chunk_msg(). This
can be shared with submit_control_msg() to reduce code duplication, and
allow control messages larger than maxpacket.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Thu, 9 Apr 2015 03:27:49 +0000 (21:27 -0600)]
usb: fix first descriptor fetch error handling
When fetching the first descriptor from a new device, only validate that
we received at least 8 bytes, not that we received the entire descriptor.
The reasoning is:
- The code only uses fields in the first 8 bytes, so that's all we need
to have fetched at this stage.
- The smallest maxpacket size is 8 bytes. Before we know the actual
maxpacket the device uses, the USB controller may only accept a single
packet (see the DWC2 note in the comment added in the commit).
Consequently we are only guaranteed to receive 1 packet (at least 8
bytes) even in a non-error case.
Fixes: 1a7758044b04 ("usb: Early failure when the first descriptor read
fails or is invalid") Cc: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
usb: Early failure when the first descriptor read fails or is invalid
This may happen when using an USB1 device on a controller that only supports
USB2 (e.g. EHCI). Reading the first descriptor will fail (read 0 byte), so we
can abort the process at this point instead of failing later and wasting time.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This checks that a new USB device is correctly initialized and frees it if not.
In addition, this doesn't report that USB was started when no device was found.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
usb_storage:Fix USB storage capacity detection on 64 bit architectures
This patch fixes USB storage capacity detection breakage on 64-bit systems
which arises due to 'unsigned long' length difference. Old code assumes that
to be 32 bit and breaks because of inappropriate response buffer layout.
Also this fixes a number of build warnings and changes big-endian values
treatment style to be architecture-independent
This commit allows xHCI to use both 64 and 32 bit memory
physical addresses depending on architecture it's being built for.
Also it makes use of readq()/writeq() on 64-bit systems
Since commit 79d75d752717 (ARM: move -march=* and -mtune= options to
arch/arm/Makefile), all the Tegra boards are broken because the SPL
is built for ARMv7.
Insert Tegra-specific code to arch/arm/Makefile to set compiler
flags for an earlier ARM architecture.
Note:
The v1 patch for commit 79d75d752717 *was* correct when it was
submitted. Notice it was originally written for multi .config
configuration where Kconfig set CONFIG_CPU_V7/CONFIG_CPU_ARM720T for
Tegra U-Boot Main/SPL, respectively. But, until it was merged into
the mainline, commit e02ee2548afe (kconfig: switch to single .config
configuration) had been already applied there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Stephen Warren <swarren@nvidia.com> Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Stefan Roese [Wed, 11 Mar 2015 11:05:04 +0000 (12:05 +0100)]
arm: armada-xp: Fix SPL for AXP by using save_boot_params_ret
Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
While testing "arc: make sure _start is in the beginning of .text
section" I haven't done proper clean-up of built binaries and so missed
another tiny bit that lead to the following error:
--->8---
LD u-boot
arc-linux-ld.bfd: cannot find arch/arc/lib/start.o
Makefile:1107: recipe for target 'u-boot' failed
make: *** [u-boot] Error 1
--->8---
This consolidates the flash settings for the Integrator
and activates the new ARM flash image support for them
so images can be loaded by name from flash.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This modifies the vexpress64 Juno configuration so that
it will by default load and boot a kernel and a device tree
from the images stored in the NOR flash. When we are
at it, also define the proper command line for the Juno and
indicate that the USB stick (/dev/sda1) is the default
root file system.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ARM reference designs all use a special flash image format
that stores a footer (two versions exist) at the end of the last
erase block of the image in flash memory.
Version one of the footer is indicated by the magic number
0xA0FFFF9F at 12 bytes before the end of the flash block and
version two is indicated by the magic number 0x464F4F54 0x464C5348
(ASCII for "FLSHFOOT") in the very last 8 bytes of the erase block.
This command driver implements support for both versions of the
AFS images (the name comes from the Linux driver in drivers/mtd/afs.c)
and makes it possible to list images and load an image by name into
the memory with these commands:
afs - lists flash contents
afs load <image> - loads image to address indicated in the image
afs load <image> <addres> - loads image to a specified address
This image scheme is used on the ARM Integrator family, ARM
Versatile family, ARM RealView family (not yet supported in U-Boot)
and ARM Versatile Express family up to and including the new
Juno board for 64 bit development.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Agner [Fri, 10 Apr 2015 09:25:43 +0000 (11:25 +0200)]
common, ubi: use positive return values for ubi check
The ubi check command is expected to not fail and just check whether
a volume exist or not. Currently, when a volume does not exist, the
command fails which leads to an error:
"exit not allowed from main input shell."
Use 1 to indicate that a volume does not exist. This allows to use
ubi check in an if statement, e.g.
if ubi check rootfs; then; echo "exists"; else; echo "not there"; fi
arc: make sure _start is in the beginning of .text section
This is important to have entry point in the beginning of .text section
because it allows simple loading and execution of U-Boot.
For example pre-bootloader loads U-Boot in memory starting from offset
0x81000000 and then just jumps to the same address.
Otherwise pre-bootloader would need to find-out where entry-point is. In
its turn if it deals with binary image of U-Boot there's no way for
pre-bootloader to get required value.
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
There're 2 versions of motherboards that could be used in ARC SDP.
The only important difference for U-Boot is different NAND IC in use:
[1] v2 board (we used to support up until now) sports MT29F4G08ABADAWP
while
[2] v3 board sports MT29F4G16ABADAWP
They are almost the same except data bus width 8-bit in [1] and 16-bit
in [2]. And for proper support of 16-bit data bus we have to pass
NAND_BUSWIDTH_16 option to NAND driver core - which we do now knowing
board type we're running on.
Prior to commit 326a682358c1, Zynq boards enabled CONFIG_DM, but
not CONFIG_SYS_MALLOC_F. That commit forcibly turned on
CONFIG_SYS_MALLOC_F. I have not figured out the root cause, but
anyway it looks like CONFIG_SYS_MALLOC_F gave a bad impact on the
Zynq MMC boot.
We are planning to have the v2015.04 release in a few days.
I know this is a defensive fixup, but what I can do now is to add
# CONFIG_SYS_MALLOC_F is not set
to every Zynq defconfig file to get back the original behavior.
Tested on:
- Zedboard
- ZC706 board
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org>
Ulises Cardenas [Fri, 27 Mar 2015 14:08:57 +0000 (08:08 -0600)]
Fix mxc_hab documenation for DEK blob generation
Include/fsl_sec.h defines sec_in and sec_out, according to the
platform's endianess. Therefore, CONFIG_SYS_FSL_LE needs to be
declared in the configuration file of the target, in order to use
enable the DEK blob generation command. This requirement is not
explicit in the README.mxc_hab.
Tom Rini [Tue, 7 Apr 2015 13:38:54 +0000 (09:38 -0400)]
cmd_mem.c: Update 'iteration_limit' to unsigned long
With e37f1eb we now use strict_strtoul() in do_mem_mtest() and this
gives us a warning:
../include/vsprintf.h:38:5: note: expected 'long unsigned int *' but
argument is of type 'int *'
MAKEALL: fix get_target_arch() to adjust to '-' in Status field
Since the Kconfig conversion, boards.cfg scanned by MAKEALL is
generated by tools/genboardscfg.py. Every board is supposed to have
its own MAINTAINERS that contains maintainer and status information,
but, in fact, MAINTAINERS is missing from some boards.
For such boards, the first field, Status, is filled with '-'.
It causes a problem for "set" command, which ignores '-' in its
arguments. Consequently, get_target_arch() returns a wrong field
and MAKEALL fails to get a correct toolchain.
kbuild: include config.mk when auto.conf is not older than .config
Since the Kconfig conversion, config.mk has been included only when
include/config/auto.conf is newer than the .config file.
It causes build error if both files have the same time-stamps.
It is actually possible because EXT* file systems have a 1s time-stamp
resolution.
The config.mk should be included when include/config/auto.conf is
*not older* than the .config file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Tom Rini <trini@konsulko.com> Reported-by: York Sun <yorksun@freescale.com> Reported-by: Stephen Warren <swarren@nvidia.com> Reported-by: Matthew Gerlach <mgerlach@opensource.altera.com> Tested-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Thu, 2 Apr 2015 20:01:33 +0000 (16:01 -0400)]
am33xx/ddr.c: Fix regression on DDR2 platforms
Back in fc46bae a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms. This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence. This change
brings us back to the older behavior and is fine on all platforms.
Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM
Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tang Yuantian [Tue, 31 Mar 2015 07:02:43 +0000 (15:02 +0800)]
ahci: Fix a wrong parameter pass
In stead of user_buffer_size, transfer_size should be used to pass to
ahci_device_data_io(). transfer_size is the length that we want the
low level function to transfer each time.
If we use user_buffer_size which is the totally data length as parameter,
low level function will actually create many SGs to transfer as many data
as possible each time. That will produce many redundant data transfer.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Mario Schuknecht [Tue, 24 Mar 2015 07:59:00 +0000 (08:59 +0100)]
env_sf: Fix recovery default
The u-boot environment is redundantly stored in a NOR flash on our boards.
Redundant means that there are two places to store the environment. But only
one of the two is active. I discovered that on one board the u-boot (env_sf)
uses the environment from the second place and the Kernel (fw_printenv) uses
the environment from the first place.
To decide which is the active environment there is a byte inside the
environment. 1 means active and 0 means obsolete. But on that board both
environments had have a 1. This can happen if a power loss or reset occurs
during writing the environment. In this situation the u-boot (env_sf)
implementation uses the second environment as default. But the Kernel
(fw_printenv) implementation uses the first environment as default.
This commit corrects the default in the u-boot env_sf implementation when a
problem was detected. Now the recovery default is the same like in all other
environment implementations. E.g. fw_printenv and env_flash. This ensures that
u-boot and Kernel use the same environment.
Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
config: exynos: common: Provide env variables to support Image.itb
This change allows using Image.itb image format with Exynos4 devices
(especially trats and trats2).
Such change facilitates automated testing since only one binary needs
to be prepared.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Ajay Kumar [Wed, 4 Mar 2015 13:35:25 +0000 (19:05 +0530)]
Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The peach boards have their SDRAM start address at 0x20000000 instead of
0x40000000 which seems common for all other exynos5 based boards. This
means the layout set in exynos5-common.h causes the kernel be loaded
more then 128MB (at 0x42000000) away from memory start which breaks
booting kernels with CONFIG_AUTO_ZRELADDR
Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses
the same offsets from start of memory as the common exynos5 settings.
This fixes booting via bootz and PXE
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Guillaume GARDET [Wed, 11 Mar 2015 09:34:27 +0000 (10:34 +0100)]
Exynos: Clock: Fix exynos5_get_periph_rate for I2C.
Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).
Changes in V2: reorder lines as requested by Joonyoung Shim.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Hans de Goede [Sat, 4 Apr 2015 08:37:44 +0000 (10:37 +0200)]
sunxi: Fix Orangepi_mini dtb filename
The Orangepi_mini is different enough from the regular Orangepi that it needs
its own dtb, but when it got added a copy and paste error was made and it
got the same dtb filename, fix this.
While at it also add a short description of both Orangepi boards to the
defconfig files for them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Alexey Brodkin [Mon, 30 Mar 2015 10:36:04 +0000 (13:36 +0300)]
arc: add support for SLC (System Level Cache, AKA L2-cache)
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidate
For now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)
Alexey Brodkin [Tue, 17 Mar 2015 11:26:43 +0000 (14:26 +0300)]
arc: minor fixes in Kconfig
[1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line
lenth selection is correctly enabled if either I$ or D$ are enabled.
[2] Add dummy entry to target list to make sure target type is always
mentioned in defconfig. Otherwise defconfig for the first target in the
list will not have target name and later on with addition of the new
target on top of the list in Kconfig will lead to corrupted
configuration expanded from defconfig.
Alexey Brodkin [Tue, 17 Mar 2015 11:30:59 +0000 (14:30 +0300)]
arc: re-generate defconfigs
Before that moment our defconfigs were manually modified with addition
of new options. That means once anybody wants to add another option and
re-genarate defconfig with "make defconfig" there will be lots of
differences. So to make future modifications more clean we'll do bulk
re-generation right away.
Alexey Brodkin [Tue, 24 Feb 2015 14:08:44 +0000 (17:08 +0300)]
arc: move low-level interrupt and exception handlers in a separate file
This separation makes maintenance of code easier because those low-level
interrupt- or exception handling routines are pretty static and usually
require not much care while start-up code is a subject of modifications
and enhancements.
Alexey Brodkin [Thu, 19 Feb 2015 15:40:58 +0000 (18:40 +0300)]
arc: merge common start-up code between ARC and ARCv2
Even though ARCompact and ARCv2 are not binary compatible most of
assembly instructions are used in both. With this change we'll get rid
of duplicate code.
Still IVTs are implemented differently so we're keeping them in separate
files.
Alexey Brodkin [Fri, 27 Mar 2015 09:47:29 +0000 (12:47 +0300)]
arc: cache - build invalidate_icache_all() and invalidate_dcache_all()
always
Make both invalidate_icache_all() and invalidate_dcache_all() available
even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or
CONFIG_SYS_ICACHE_OFF.
This is useful because configuration of U-Boot may not match actual
hardware features. Real board may have cache(s) but for some reason we
may want to run U-Boot with cache(s) disabled (for example if some
peripherals work improperly with existing drivers if data cache is
enabled). So board may start with cache(s) enabled (that's the case for
ARC cores with built-in caches) but early in U-Boot we disable cache(s)
and make sure all contents of data cache gets flushed in RAM.
projects / karo-tx-uboot.git / log