Jonghwan Choi [Fri, 16 May 2014 23:19:30 +0000 (08:19 +0900)]
cpufreq: exynos: Fix the compile error
Commit 7da83a80 ("ARM: EXYNOS: Migrate Exynos specific macros from
plat to mach") which lands in samsung tree causes build breakage
for cpufreq-exynos like following:
drivers/cpufreq/exynos-cpufreq.c: In function 'exynos_cpufreq_probe':
drivers/cpufreq/exynos-cpufreq.c:166:2: error: implicit declaration of function 'soc_is_exynos4210'
[-Werror=implicit-function-declaration]
drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4212'
[-Werror=implicit-function-declaration]
drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4412'
[-Werror=implicit-function-declaration]
drivers/cpufreq/exynos-cpufreq.c:170:2: error: implicit declaration of function 'soc_is_exynos5250'
[-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[2]: *** [drivers/cpufreq/exynos-cpufreq.o] Error 1
make[2]: *** Waiting for unfinished jobs....
drivers/cpufreq/exynos4x12-cpufreq.c: In function 'exynos4x12_set_clkdiv':
drivers/cpufreq/exynos4x12-cpufreq.c:118:2: error: implicit declaration of function 'soc_is_exynos4212'
[-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[2]: *** [drivers/cpufreq/exynos4x12-cpufreq.o] Error 1
make[1]: *** [drivers/cpufreq] Error 2
This fixes above error with getting SoC information via
of_machine_is_compatible() instead of soc_is_exynosXXXX().
Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
[kgene.kim@samsung.com: fixed typo and modified as per Viresh's suggestion]
[kgene.kim@samsung.com: Rafael agreed] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Chanwoo Choi [Fri, 16 May 2014 22:37:37 +0000 (07:37 +0900)]
dt-bindings: add documentation for Exynos3250 clock controller
The Exynos3250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Randy Dunlap <rdunlap@infradead.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Kukjin Kim [Fri, 16 May 2014 22:10:49 +0000 (07:10 +0900)]
Merge branch 'for_3.16/exynos5260' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into v3.16-next/clk-samsung
Pull Samsung clock exynos5260 from Tomasz Figa:
"This pull request contains patches preparing Samsung Common Clock Framework
helpers to support Exynos5260 by adding support for multiple clock providers
and then adding clock driver for Exynos5260."
Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 15 May 2014 21:59:18 +0000 (06:59 +0900)]
ARM: S3C24XX: trim down debug uart handling
Using the lowlevel debug uart is a corner case - even more so in a
multiplatform environment. So it seems reasonable to simply let the
developer set the appropriate uart type for the debugged SoC.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 15 May 2014 21:59:18 +0000 (06:59 +0900)]
ARM: compressed/head.S: remove s3c24xx special case
addruart from the generic debug macro is doing exactly the same using
the common lowlevel uart definition, so there is no cause for this
special casing for s3c24xx.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Vivek Gautam [Thu, 15 May 2014 21:38:15 +0000 (06:38 +0900)]
ARM: dts: Update DWC3 usb controller to use new phy driver for exynos5250
Removing the dt node for older usb3 phy driver from Exynos5250
device tree and updating the dt node for DWC3 controller to
use new phy driver based on generic phy framework.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Rahul Sharma [Thu, 15 May 2014 20:23:16 +0000 (05:23 +0900)]
ARM: dts: change to correct compatible string for exynos5420 hdmi
Replace compatible string for HDMI node in Exynos5420. Since
latest restructring in Drm hdmi driver, it is agreed to use
a seperate compatible string for Exynos5420 HDMI IP siince it
uses APB mapped Phy.
Signed-off-by: Rahul Sharma <Rahul.Sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Wed, 14 May 2014 19:17:17 +0000 (04:17 +0900)]
ARM: dts: Remove g2d_pd node for exynos5420
G2D power domain also controls the CMU block of G2D. Since
clock registers can be accessed anytime for viewing
clk_summary, it can cause a system crash if g2d power domain
is disabled.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tushar Behera [Wed, 14 May 2014 19:16:03 +0000 (04:16 +0900)]
ARM: dts: Remove mau_pd node for exynos5420
MAU powerdomain provides clocks for Audio sub-system block.
This block comprises of the I2S audio controller, audio DMA
blocks and Audio sub-system clock registers.
Right now, there is no way to hook up power-domains with
clock providers. During late boot when this power-domain
gets disabled, we get following external abort.
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Sachin Kamat [Wed, 14 May 2014 19:14:16 +0000 (04:14 +0900)]
ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount
High speed I2C is used on Exynos5 based SoCs. Enable it.
The MMC partition for Root filesystem cannot be mounted
without this enabling HS-I2C and regulators on many boards
are connected HS-I2C bus so the regulators don't come by
default without this.
Actually, we are not able to get arndale-octa board to boot
and mount an MMC partition without this change.
Seungwon Jeon [Thu, 8 May 2014 22:02:33 +0000 (07:02 +0900)]
ARM: dts: disable MDMA1 node for exynos5420
This change places MDMA1 in disabled node for Exynos5420.
If MDMA1 region is configured with secure mode, it makes
the boot failure with the following on smdk5420 board.
("Unhandled fault: imprecise external abort (0x1406) at 0x00000000")
Thus, arndale-octa board don't need to do the same thing anymore.
Sachin Kamat [Mon, 12 May 2014 22:13:44 +0000 (07:13 +0900)]
ARM: EXYNOS: Map SYSRAM through generic DT bindings
Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Tue, 13 May 2014 13:05:06 +0000 (22:05 +0900)]
clk: samsung: exynos3250: Add clocks using common clock framework
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.
The CMU of Exynos3250 includes following clock doamins:
- CPU block for Cortex-A7 MPCore processor
- LEFTBUS/RIGHTBUS block
- TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Karol Wrona <k.wrona@samsung.com> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
Pankaj Dubey [Thu, 8 May 2014 04:07:11 +0000 (13:07 +0900)]
drivers: clk: use COMMON_CLK_SAMSUNG for Samsung clock support
This patch replaces PLAT_SAMSUNG with COMMON_CLK_SAMSUNG for Samsung
common clock support. Any Samsung SoC want to use Samsung common clock
infrastructure can simply select COMMON_CLK_SAMSUNG.
CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch moves S3C24XX specific clock Kconfig options into
"clk/samsung/Kconfig" and also removes COMMON_CLK selection from
"mach-s3c24xx/Kconfig" as S3C24XX_COMMON_CLK is selecting it's dependency.
CC: Ben Dooks <ben-linux@fluff.org> CC: Kukjin Kim <kgene.kim@samsung.com> CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
clk: samsung: exynos5420: update clocks for PERIC block
This patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet
3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block
5] use GATE_IP_* offsets instead of GATE_BUS_*
This patch renames the mux parent arrays as per the naming
convension followed by the other exynos specific clock drivers.
And it also renames "mout_cpu_kfc" clock to "mout_kfc".
This patch adds the required clocks for ARM Mali IP
in Exynos5250.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
[t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocks
Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock
defined exactly in same way in documentation. Using different
names for these clocks is a bit misleading. Since there is no users
of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and
replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA
has correct clock assigned on Exynos4x12 SoCs.
Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
clk: samsung: exynos5250/5420: Add gate clock for SSS module
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Thu, 6 Feb 2014 18:33:11 +0000 (19:33 +0100)]
clk: samsung: Initialize clock table with error pointers
Before this patch, the driver was simply zeroing the clock table, which
is incorrect, because invalid clock numbers returned NULL instead of
error pointers. This patch fixes this by changing the driver to
initialize the array with PTR_ERR(-ENOENT).
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Rahul Sharma [Wed, 12 Mar 2014 14:56:44 +0000 (20:26 +0530)]
clk/samsung: add support for multiple clock providers
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.
This layer is modified accordingly to enable the support
for multiple clock providers.
Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c24xx are also modified as per changed helper functions.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
[t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Heiko Stuebner [Thu, 8 May 2014 20:49:19 +0000 (05:49 +0900)]
ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework
Convert all machines using these cpus to use the ccf clock driver
instead of the legacy Samsung clock implementation.
Some of the more esotheric machines will probably need a fixup, as they
do strange things to the clkout outputs, that I did not really understand
nor have the hardware to check.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 8 May 2014 20:49:14 +0000 (05:49 +0900)]
ARM: S3C24XX: add platform code for conversion to the common clock framework
This adds the necessary init functions to init the clocks from the common
clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy
clock code.
This also includes empty stubs for the *_setup_clocks functions that are
called from the cpufreq driver on resume.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 8 May 2014 20:49:10 +0000 (05:49 +0900)]
clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442
This driver can handle the clock controllers of the socs mentioned above,
as they share a common clock tree with only small differences.
The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.
As pll-rate-tables only the 12mhz variants are currently included.
The original code was wrongly checking for 169mhz xti values [a 0 to much
at the end], so the original 16mhz pll table would have never been
included and its values are so obscure that I have no possibility to
at least check their sane-ness. When using the formula from the manual
the resulting frequency is near the table value but still slightly off.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 8 May 2014 20:48:57 +0000 (05:48 +0900)]
ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.
This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.
The machine-specific settings for the external clocks will have to be set
by somebody with knowledge about the specific hardware.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
[pebolle@tiscali.nl: pointed out typo and fixed] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Sun, 11 May 2014 22:56:34 +0000 (07:56 +0900)]
ARM: dts: Add exynos5800-peach-pi board support
Adds support for google peach-pi board having the
Exynos5800 SoC.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Sun, 11 May 2014 22:55:41 +0000 (07:55 +0900)]
ARM: dts: Add exynos5800 dt file
Most of the nodes of exynos5420 remains same for exynos5800.
So the exynos5420.dtsi is included in exynos5800 and the changed
node properties will be overriden.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
A common macro v7_exit_coherency_flush available which does the below
tasks in the seqeunce.
-clearing C bit
-clearing L1 cache
-exit SMP
-instruction and data synchronization
So removing the local functions which does the same thing and use the
macro instead.
Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org>
[cw00.choi@samsung.com: tested on exynos3250 based board] Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Thu, 8 May 2014 21:06:25 +0000 (06:06 +0900)]
ARM: dts: Add exynos5420 peach-pit board support
Adds the google peach-pit board dts file which uses
exynos5420 SoC.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Thu, 8 May 2014 21:06:24 +0000 (06:06 +0900)]
ARM: dts: Add node labels to exynos5420
Adding labels to nodes which do not have it yet in exynos5420.
This is done so as to use reference based node updation in board
files.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arun Kumar K [Thu, 8 May 2014 21:06:10 +0000 (06:06 +0900)]
ARM: dts: Add pwmX_out pinctrl nodes to exynos5420
Adds the PWM nodes to 5420 pinctrl dtsi file.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
ARM: dts: Add rear camera nodes for exynos4412-trats2
This patch enables the rear facing camera (s5c73m3) on TRATS2 board
by adding the I2C0 bus controller, s5c73m3 sensor, MIPI CSI-2 receiver
and the sensor's voltage regulator supply nodes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
ARM: dts: Update camera nodes for exynos4 and exynos4412-trats2
Remove unused /camera/clock-controller node and add required clock
properties to the camera node. This is required for a clock provider
that will be referenced by image sensor devices.
Also add required clock related changes to s5k6a3 device node and
afvdd regulator supply.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
ARM: dts: rename alias for i2c_ak8975 label for exynos4412-trats2
The i2c_ak8975 controller uses label i2c8.
This alias is already used for I2C controller 8 defined
in file arch/arm/boot/dts/exynos4.dtsi.
This patch renames a label for i2c_ak8975 to i2c9.
Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing pinctrls for I2C controllers 2-7.
Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 8 May 2014 20:48:51 +0000 (05:48 +0900)]
clk: samsung: add clock driver for external clock outputs
This adds a driver for controlling the external clock outputs of
s3c24xx architectures including the dclk muxes and dividers.
The driver at the moment only supports the legacy non-dt boards using these
clock outputs. The clock-output control itself is part of the system-controller
mainly controlled by the pinctrl drivers. So it should most likely be
integrated there for dt platforms.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
projects / karo-tx-linux.git / log