Andrew Ruder [Wed, 12 Aug 2015 18:18:31 +0000 (13:18 -0500)]
arm: pxa: use common timer functions
This patch moves pxa to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor. Rather than patch the specific pxa issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
Andrew Ruder [Wed, 12 Aug 2015 17:55:47 +0000 (12:55 -0500)]
pxa: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors")
pxa does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.
This allows pxa to boot again.
Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Marek Vasut [Wed, 19 Aug 2015 05:46:49 +0000 (07:46 +0200)]
arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Marek Vasut [Mon, 10 Aug 2015 15:20:23 +0000 (17:20 +0200)]
arm: socfpga: dts: Add bank-name property to each GPIO bank
Add "bank-name" property to each GPIO bank to give it unique name.
The approach here is exactly the same as with the "regulator-name"
property for regulators.
Marek Vasut [Mon, 10 Aug 2015 20:17:46 +0000 (22:17 +0200)]
arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Marek Vasut [Mon, 10 Aug 2015 18:48:07 +0000 (20:48 +0200)]
arm: socfpga: Add qts-filter.sh script
Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.
Marek Vasut [Mon, 10 Aug 2015 19:24:53 +0000 (21:24 +0200)]
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Marek Vasut [Sun, 2 Aug 2015 19:57:57 +0000 (21:57 +0200)]
arm: socfpga: Unbind CPU type from board type
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.
All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.
The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.
Marek Vasut [Sun, 2 Aug 2015 19:12:09 +0000 (21:12 +0200)]
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Marek Vasut [Mon, 3 Aug 2015 13:32:37 +0000 (15:32 +0200)]
arm: socfpga: Do not enable gmac1 in Cyclone V dtsi
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.
Marek Vasut [Sun, 2 Aug 2015 20:55:24 +0000 (22:55 +0200)]
arm: socfpga: Make the DT mmc node consistent
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
Marek Vasut [Mon, 10 Aug 2015 22:54:12 +0000 (00:54 +0200)]
arm: socfpga: Fix delay in clock manager
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Marek Vasut [Mon, 10 Aug 2015 22:49:09 +0000 (00:49 +0200)]
arm: socfpga: Fix delay in freeze controller
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.
Marek Vasut [Mon, 10 Aug 2015 21:01:43 +0000 (23:01 +0200)]
ddr: altera: Repair uninited variable
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (found_passing_read && found_failing_read)
^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
u32 found_passing_read, found_failing_read, initial_failing_dtap;
^
Marek Vasut [Mon, 10 Aug 2015 20:50:11 +0000 (22:50 +0200)]
ddr: altera: Replace float multiplication with integer one
This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.
Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.
This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.
Simon Glass [Wed, 19 Aug 2015 15:33:42 +0000 (09:33 -0600)]
Tidy up some defconfig files
Several files are out of order. This means that when the moveconfig tool
moves CONFIG options to Kconfig it generates a large diff. To avoid this,
reorder the files first.
Simon Glass [Wed, 19 Aug 2015 15:33:39 +0000 (09:33 -0600)]
net: e1000: Prepare for driver model conversion
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.
Also refactor the code so that code that the driver model implementation
will share are available in functions that can be called. Add stubs where
necessary.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
Michal Simek [Fri, 21 Aug 2015 06:49:48 +0000 (08:49 +0200)]
net: Return -EINTR when ctrl+c is pressed
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is "tftpboot 80000 uImage && echo yes"
and press CTRL+C. Then the second command is called which is incorrect.
Error log:
zynq-uboot> tftpb 80000 uImage && echo yes
Gem.e000b000:7 is connected to Gem.e000b000. Reconnecting to
Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete....... done
Using Gem.e000b000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.101
Filename 'uImage'.
Load address: 0x80000
Loading: ################
Abort
yes
zynq-uboot>
This patch adds -EINTR return value when CTRL+C is pressed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mingkai Hu [Tue, 18 Aug 2015 21:06:26 +0000 (14:06 -0700)]
net: e1000: Support 64-bit physical address
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Pavel Machek [Tue, 18 Aug 2015 12:34:26 +0000 (14:34 +0200)]
tftp: adjust settings to be suitable for 100Mbit ethernet
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.
100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets. Timeout count really needs to be way higher,
as lost packets are normal when TCP is running over the same network.
Enforce 10msec minimum.
Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Wu, Josh [Wed, 19 Aug 2015 11:11:21 +0000 (19:11 +0800)]
ARM: at91: sama5: update the spi flash mapping
Also move the spi flash configurations to the at91-sama5_common.h.
Current at91 zImage size is about 3.3M, the old mapping is not
suitable. So update the spi flash map as following:
0x0 ~ 0x004000: at91bootstrap(16k)
0x04000 ~ 0x008000: u-boot env(16k)
0x08000 ~ 0x060000: u-boot(352k)
0x60000 ~ 0x06c000: dtb (48k)
0x6c000 ~ 0x400000: kernel (3M+592k)
In AT91Bootstrap, the U-Boot in spi flash also update to 0x8000, refer
to following commit in AT91Bootstrap: 3e91e54 Kconfig: fix spi flash address
So also update SPL's u-boot load address to 0x8000 in spi flash.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Erik van Luijk [Thu, 13 Aug 2015 13:43:18 +0000 (15:43 +0200)]
arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Chris Packham [Tue, 14 Jul 2015 10:54:41 +0000 (22:54 +1200)]
mips: Use unsigned int when reading c0 registers
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).
Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).
The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.
Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com>
populate _reset_ callback to the USB ethernet gadget since UDC core
expects every gadget driver to have the reset callback. This shouldn't
be needed once the ethernet gadget driver is adapted to use the
composite driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stop
xhci omap driver has board_usb_init in xhci_hcd_init but doesn't have
the corresponding cleanup function in xhci_hcd_stop.
Fix it here by invoking board_usb_cleanup() in xhci_hcd_stop().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: gadget: ether: Perform board initialization from ethernet gadget driver
Ethernet gadget driver can be used both by both SPL and u-boot. Since
usb_eth_init() is the entry point for ethernet gadget driver, perform
board initialization there. Also perform the cleanup in usb_eth_halt.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: xhci: Fix a potential NULL pointer dereference
This patch fixes a potential NULL pointer dereference arising on
non-present/non-initialized xHCI controllers and adds some error
handling to xHCI code
Stefan Roese [Tue, 18 Aug 2015 07:27:18 +0000 (09:27 +0200)]
usb: spear: Add support for both SPEAr600 EHCI controllers
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Marek Vasut <marex@denx.de>
Michal Simek [Wed, 12 Aug 2015 09:25:05 +0000 (11:25 +0200)]
ARM: dts: Rename memory@0 to memory
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.
Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynqmp: usb: Add usb dwc3 driver support for zynqmp
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Sat, 1 Aug 2015 07:39:54 +0000 (16:39 +0900)]
ARM: zynq: drop "optional" from board select in favor of ZC702
One disadvantage of commit a26cd04920dc (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
Rip off the "optional" again in favor of ZC702 as the default
target.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Aug 2015 05:50:16 +0000 (07:50 +0200)]
ARM: zynqmp: Add platform specific arch_get_page_table
Based on the patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1: dad17fd51027ad02ac8f02deed186d08109d61fd)
it is necessary to add platform specific hook.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:55 +0000 (07:31 +0900)]
of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:
Masahiro Yamada [Tue, 11 Aug 2015 22:31:54 +0000 (07:31 +0900)]
of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:52 +0000 (07:31 +0900)]
dm: drop CONFIG_DM_DEVICE_REMOVE from uncmd list
We do not want to compile the DM remove code for SPL. Currently,
we undef it in include/config_uncmd_spl.h (for C files) and in
scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly.
This commit demonstrates how we can deprecate those two files.
Use $(SPL_) for the entry in the Makfile and CONFIG_IS_ENABLED()
in C files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:44 +0000 (07:31 +0900)]
spl: move SPL driver entries to driver/Makefile
Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:43 +0000 (07:31 +0900)]
linux/kconfig.h: add CPP macros useful for per-image config options
The previous commit introduced a useful macro used in makefiles,
in order to reference to different variables (CONFIG_... or
CONFIG_SPL_...) depending on the build context.
Per-image config option control is a PITA in C sources, too.
Here are some macros useful in C/CPP expressions.
CONFIG_IS_ENABLED(FOO) can be used as a shorthand for
For example, it is useful to describe C code as follows,
#if CONFIG_IS_ENABLED(OF_CONTROL)
(device tree code)
#else
(board file code)
#endif
The ifdef conditional above is switched by CONFIG_OF_CONTROL during
the U-Boot proper building (CONFIG_SPL_BUILD is not defined), and by
CONFIG_SPL_OF_CONTROL during SPL building (CONFIG_SPL_BUILD is
defined).
The macro can be used in C context as well, so you can also write the
equivalent code as follows:
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
(device tree code)
} else {
(board file code)
}
Another useful macro is CONFIG_VALUE().
CONFIG_VALUE(FOO) is expanded into CONFIG_FOO if CONFIG_SPL_BUILD is
undefined, and into CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
This commit also adds slight hacking on fixdep so that it can
output a correct list of fixed dependencies.
If the fixdep finds CONFIG_IS_ENABLED(FOO) in a source file,
we want
$(wildcard include/config/foo.h)
in the U-boot proper building context, while we want
$(wildcard include/config/spl/foo.h)
in the SPL build context.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:42 +0000 (07:31 +0900)]
kbuild: add a makefile macro useful with per-image config options
Commit e02ee2548afe ("kconfig: switch to single .config
configuration") made the configuration itself pretty simple,
instead, we lost the way to systematically enable/disable config
options for each image independently.
Our current strategy is, put entries into Makefile.spl for options
we need separate enabling, or once enable the options globally in
Kconfig and then undef them in Makefile.uncmd_spl if we do not want
to compile the features for SPL at all. Things are getting really
messy. Besides, "ifdef CONFIG_SPL_BUILD" are sprinkled everywhere
in makefiles.
This commit adds a variable to help describe makefile simpler.
$(SPL_) evaluates to "SPL_" during the SPL build, while to an empty
string during building U-boot proper.
This is the pattern we often see in our current makefiles.
To take advantage of this macro, we should prefix SPL_ for the SPL
version of the option when we need independent control between
U-boot and SPL. With this naming scheme, I hope our makefiles will
be much simplified.
It means we want to rename existing config options as follows
in the long run:
Stephen Warren [Tue, 11 Aug 2015 04:45:14 +0000 (22:45 -0600)]
fs-test.sh: minor fixes
- Re-direct stderr into the log files, so any errors U-Boot emits are
visible in the logs. This is relevant if the "reset" shell command
attempts to report that it's not supported on the sandbox board.
- Fix test_fs_nonfs() to name the files it created differently for each
invocation. Otherwise, the logs from different tests overwrite
each-other.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Suriyan Ramasami <suriyan.r@gmail.com>
i2c: lpc32xx: correct sanity check for requested bus speed
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones
and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit
wide. This means that if HCLK is 104MHz, then minimal configurable I2C
clock speed is about 51KHz.
Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in
assumption that peripheral clock is 13MHz it allows to set the minimal
bus speed about 25.5KHz.
Check for negative half clock value is removed since it is always false.
The change fixes the following problem for I2C busses 0 and 1:
=> i2c dev 0
Setting bus to 0
=> i2c speed 100000
Setting bus speed to 100000 Hz
Failure changing bus speed (-22)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Thu, 13 Aug 2015 19:40:22 +0000 (15:40 -0400)]
usb: lpc32xx: add host USB driver
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Sylvain Lemieux [Thu, 13 Aug 2015 19:40:21 +0000 (15:40 -0400)]
nand: lpc32xx: add ECC layout for small page NAND
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This layout is matching the lpc32xx NAND SLC Linux Kernel driver.
lpc32xx: move common SLC NAND defines to arch/config.h
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h
The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Vignesh R [Mon, 17 Aug 2015 07:59:57 +0000 (13:29 +0530)]
ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With
DMA enabled there is almost 3x improvement in read performance. This
helps in reducing boot time in qspiboot mode
Also add EDMA3 base address for DRA7XX and AM57XX.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Mon, 17 Aug 2015 07:59:54 +0000 (13:29 +0530)]
sf: ops: Add spi_flash_copy_mmap function
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
projects / karo-tx-uboot.git / log