Stefan Roese [Mon, 9 Nov 2009 13:13:43 +0000 (14:13 +0100)]
ppc4xx: Switch to I2C bus numer 0 for chip_config command
All currently available 4xx derivats have the I2C bootstrap EEPROM
located on I2C bus number 0. This patch now first sets this bus number,
so that the chip_config command also works for board with multiple
I2C busses, like Katmai.
Stefan Roese [Thu, 29 Oct 2009 15:54:52 +0000 (16:54 +0100)]
ppc4xx: Remove duplicated is_pci_host() functions
This patch introduces a weak default function for is_pci_host(),
returning 1. This is the default behaviour, since most boards only
implement PCI host functionality. This weak default can be overridden
by a board specific version if needed.
Stefan Roese [Thu, 29 Oct 2009 14:04:35 +0000 (15:04 +0100)]
ppc4xx: Consolidate 4xx PCIe board specific configuration
This patch consolidates the PPC4xx board specific PCIe configuration
code. This way the duplicated code is removed. Boards can implement a
special, non standard behaviour (e.g. number of PCIe slots, etc) by
overriding the weak default functions.
Stefan Roese [Tue, 27 Oct 2009 15:11:26 +0000 (16:11 +0100)]
ppc4xx: Add common ppc4xx linker script
This linker script can be used by all PPC4xx platforms. It works for
PPC405 and PPC440 platforms. Boards which need a board specific linker
script can override this default linker script in board/*/config.mk.
Stefan Roese [Tue, 27 Oct 2009 15:16:13 +0000 (16:16 +0100)]
ppc4xx: Add custom linker script to board/*/config.mk
These boards have special linker scripts right now. We can't use the
common 4xx linker script here. So overrride the linker script (LDSCRIPT)
in board/*/config.mk and choose the board specific version.
Stefan Roese [Tue, 27 Oct 2009 14:57:24 +0000 (15:57 +0100)]
ppc4xx: Fix problems in some ppc4xx board Makefiles
Some 4xx Makefiles didn't add $(SOBJ) to their board library. This was
no till now problem, since those boards included this object (init.o
most of the time) directly from their linker scripts. This patch clean
this up, so that all objects are now collected in the board library. This
is in preparation for the upcoming PPC4xx linker script consolidation.
Stefan Roese [Tue, 27 Oct 2009 10:46:23 +0000 (11:46 +0100)]
mkconfig: Create board directory (CONFIG_BOARDDIR) in include/config.h
This patch extends the mkconfig script to automatically create a define
for the board directory in include/config.h:
#define CONFIG_BOARDDIR board/amcc/canyonlands
This is needed for the upcoming PPC4xx linker script consolidation,
where the PPC440 platforms need to include a board specific file in
the common linker script.
video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01
In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words
for D32 accesses due to the diffferent connecting to the GDC bus. This
patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP,
which should be set for all board using the mb862xx in 16 bpp mode. For
the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set.
video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode
The new IPEK01 board can use the 32 bpp mode for the Lime graphics
controller. For this mode, video accelaration does not work. This patch
makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL,
which is enabled for the lwmon5 and the socrates board for backward
compatibility.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.
Stefan Roese [Tue, 27 Oct 2009 14:15:55 +0000 (15:15 +0100)]
cfi: Add weak default function for flash_cmd_reset()
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
Peter Tyser [Sun, 25 Oct 2009 20:12:56 +0000 (15:12 -0500)]
Add 'editenv' command
The editenv command can be used to edit an environment variable.
Editing an environment variable is useful when one wants to tweak an
existing variable, for example fix a typo or change the baudrate in the
'bootargs' environment variable.
Peter Tyser [Sun, 25 Oct 2009 20:12:55 +0000 (15:12 -0500)]
setenv(): Delete 0-length environment variables
Previously setenv() would only delete an environment variable if it
was passed a NULL string pointer as a value. It should also delete an
environment variable when it encounters a valid string pointer of
0-length.
This change/fix is generally useful and is necessary for the upcoming
"editenv" command.
Peter Tyser [Sun, 25 Oct 2009 20:12:54 +0000 (15:12 -0500)]
readline(): Add ability to modify a string buffer
If the 'buf' parameter is a non-0-length string, its contents will be
edited. Previously, the initial contents of 'buf' were ignored and the
user entered its contents from scratch.
This change is necessary to support the upcoming "editenv" command but
could also be used for future commands which require a user to modify
an existing string.
Peter Tyser [Sun, 25 Oct 2009 20:12:52 +0000 (15:12 -0500)]
Check for NULL prompt in readline_into_buffer()
Previously, passing readline() or readline_into_buffer() a NULL 'prompt'
parameter would result in puts() printing garbage when
CONFIG_CMDLINE_EDITING was enabled.
Note that no board currently triggers this bug. Enabling
CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in
the bug appearing. This change is only intended to prevent someone
from running into this issue in the future.
Anton Vorontsov [Thu, 15 Oct 2009 13:47:13 +0000 (17:47 +0400)]
mpc85xx: Configure QE UART for MPC8569E-MDS boards
To make QE UART usable by Linux we should setup pin multiplexing
and turn UCC2 Ethernet node into UCC2 QE UART node.
Also, QE UART is mutually exclusive with UART0, so we can't enable
it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype
board with eSDHC in 1- or 4-bits mode.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Anton Vorontsov [Thu, 15 Oct 2009 13:47:06 +0000 (17:47 +0400)]
mpc85xx: Add eSDHC support for MPC8569E-MDS boards
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.
Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).
So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Peter Tyser [Fri, 23 Oct 2009 20:55:47 +0000 (15:55 -0500)]
85xx: MP Boot Page Translation update
This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
address in SDRAM. Previously, secondary cores were put into spin
loops in the 0xfffffxxx address range which required that boot page
translation was always enabled while cores were in their spin loops.
- Allow the TLB window that the primary core uses to access the
secondary cores boot page to be placed at any address. Previously, a
TLB window at 0xfffff000 was always used to access the seconary cores'
boot page. This TLB address requirement overlapped with other
peripherals on some boards (eg XPedite5370). By default, the boot
page TLB will still use the 0xfffffxxx address range, but this can be
overridden on a board-by-board basis by defining a custom
CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page
remains in use while U-Boot executes. Previously it was only
temporarily used, then restored to its initial value.
- Allow Boot Page Translation to be disabled on bootup. Previously,
Boot Page Translation was always left enabled after secondary cores
were brought out of reset. This caused the 0xfffffxxx address range
to somewhat "magically" be translated to an address in SDRAM. Some
boards may not want this oddity in their memory map, so defining
CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
the secondary cores are initialized.
These changes are only applicable to 85xx boards with CONFIG_MP defined.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Vivek Mahajan [Tue, 27 Oct 2009 06:48:55 +0000 (12:18 +0530)]
ppc/85xx/pci: fsl_pci_init: pcie agent mode support
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Anton Vorontsov [Thu, 15 Oct 2009 13:47:04 +0000 (17:47 +0400)]
fdt_support: Add multi-serial support for stdout fixup
Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX
constant. With multi-serial support, the CONS_INDEX may no longer
represent actual console, so we should try to extract port number
from the current stdio device name instead of always hard-coding the
constant value.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 22 Oct 2009 04:29:51 +0000 (23:29 -0500)]
fdt: Fix fdt padding issue for initrd mem_rsv
Its possible that we end up with a device tree that happens to be a
particular size that after we call fdt_resize() we don't have any
space left for the initrd mem_rsv.
Fix this be adding a second mem_rsv into the size calculation. We
had one to cover the fdt itself and we have the potential of adding
a second for the initrd.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Simon Kagstrom [Tue, 6 Oct 2009 06:44:22 +0000 (08:44 +0200)]
arm926ejs: 8-byte align stack to avoid LDRD/STRD problems
U-boot for Marvell Kirkwood boards no longer work after the EABI changes
introduced in commit f772acf8a584067033eff1e231fcd1fb3a00d3d9. This
turns out to be caused by a stack alignment issue. The armv5te
instructions ldrd/strd instructions require 8-byte alignment to work
properly (otherwise undefined behavior).
Tested on an OpenRD base board, where both printouts and ubifs stuff now
works.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Sandeep Paulraj [Tue, 13 Oct 2009 16:32:32 +0000 (12:32 -0400)]
TI DaVinci: Fix DM6467 EVM Compilation Warning
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.
The long term solution(after 2009.11) to this is to
have SOC specific header files.
Sandeep Paulraj [Tue, 13 Oct 2009 16:01:52 +0000 (12:01 -0400)]
TI DaVinci: DM355 Leopard: Fix compilation warning
We get a compliation warning when we enable the NAND driver
for DM355 leopard. The waring we get is that we have
an implicit declaration of davinci_nand_init.
It is fixed by including the asm/arch/nand_defs.h header file
Stefan Roese [Mon, 19 Oct 2009 14:19:36 +0000 (16:19 +0200)]
ppc4xx: Sequoia: Add chip_config command
This patch removes the Sequoia "bootstrap" command and replaces it
with the now common command "chip_config".
Please note that the patches with the dynamic PCI sync clock
configuration have to be applied, before this one should go in.
This is because Sequoia has 2 different bootstrap EEPROMs, and
the old bootstrap command configured different values depending
on the detected PCI async clock (33 vs. 66MHz). With the PCI sync
clock patches, this is not necessary anymore. The PCI sync clock
will be configured correctly on-the-fly now.
Stefan Roese [Mon, 19 Oct 2009 12:44:11 +0000 (14:44 +0200)]
ppc4xx: Print PCI synchronous clock frequency upon bootup
Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.
Stefan Roese [Mon, 19 Oct 2009 12:06:23 +0000 (14:06 +0200)]
ppc4xx: Add function to check and dynamically change PCI sync clock
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:
This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.
Stefan Roese [Fri, 16 Oct 2009 08:01:09 +0000 (10:01 +0200)]
ppc4xx: Update flash size in reg property of the NOR flash node
Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.
This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Stefan Roese [Wed, 21 Oct 2009 09:59:52 +0000 (11:59 +0200)]
fdt: Add fdt_fixup_nor_flash_size() to fixup NOR FLASH size in dtb
This function can be used to update the size in the "reg" property
of the NOR FLASH device nodes. This is necessary for boards with
non-fixed NOR FLASH sizes.
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Tue, 20 Oct 2009 21:12:13 +0000 (23:12 +0200)]
cpu/ppc4xx/fdt.c: avoid strcpy() to constant string
strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.
Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Tue, 20 Oct 2009 21:07:04 +0000 (23:07 +0200)]
cpu/ppc4xx/fdt.c: avoid strcpy() to constant string
strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.
Mike Frysinger [Mon, 19 Oct 2009 00:43:14 +0000 (20:43 -0400)]
envcrc: check return value of fwrite()
Newer toolchains will often complain about unchecked fwrite():
envcrc.c:117: warning: ignoring return value of `fwrite´, declared
with attribute warn_unused_result
So check the return value to silence the warnings.
Sandeep Paulraj [Sun, 11 Oct 2009 13:10:27 +0000 (09:10 -0400)]
TI DaVinci Sonata: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Sandeep Paulraj [Sun, 11 Oct 2009 13:14:58 +0000 (09:14 -0400)]
TI DaVinci DVEVM: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Sandeep Paulraj [Sat, 10 Oct 2009 14:19:20 +0000 (10:19 -0400)]
TI DaVinci DM365: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Sandeep Paulraj [Sat, 10 Oct 2009 14:18:46 +0000 (10:18 -0400)]
TI DaVinci DM355: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
projects / karo-tx-uboot.git / log