Fugang Duan [Wed, 6 Nov 2013 05:36:23 +0000 (13:36 +0800)]
ENGR00286416 net:fec: Pinctrl PM: add net device running status check
In below case:
ifconfig eth0 down
echo mem > /sys/power/state
After resume, fec pin status set to default, which is not expected
and cost unnecessary power. So, add net device running status check
before calling Pinctrl PM APIs.
/drivers/usb/chipidea/host.c: In function 'host_start':
/drivers/usb/chipidea/host.c:67:6: error: 'struct ehci_hcd'
has no member named 'has_tdi_phy_lpm'
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Tue, 5 Nov 2013 06:45:38 +0000 (14:45 +0800)]
usb: hcd: move controller wakeup setting initialization to individual driver
Individual controller driver has different requirement for wakeup
setting, so move it from core to itself. In order to align with
current etting the default wakeup setting is enabled (except for
chipidea host). Since too many differences between upstream with
our internal tree, I only pick the hcd change.
Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Wed, 23 Oct 2013 07:47:49 +0000 (15:47 +0800)]
ENGR00286159-1 usb: chipidea: add freescale imx28 special write register method
According to Freescale imx28 Errata, "ENGR119653 USB: ARM to USB
register error issue", All USB register write operations must
use the ARM SWP instruction. So, we implement special hw_write
and hw_test_and_clear for imx28.
Discussion for it at below:
http://marc.info/?l=linux-usb&m=137996395529294&w=2
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Wed, 23 Oct 2013 07:41:08 +0000 (15:41 +0800)]
usb: ehci: add freescale imx28 special write register method
According to Freescale imx28 Errata, "ENGR119653 USB: ARM to USB
register error issue", All USB register write operations must
use the ARM SWP instruction. So, we implement a special ehci_write
for imx28.
Discussion for it at below:
http://marc.info/?l=linux-usb&m=137996395529294&w=2
Signed-off-by: Peter Chen <peter.chen@freescale.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Peter Chen [Wed, 30 Oct 2013 01:19:29 +0000 (09:19 +0800)]
usb: chipidea: only get vbus regulator for non-peripheral mode
If the user chooses peripheral mode for this controller, the vbus
regulator doesn't need to get, since the host will supply the vbus,
it can save one vbus pin for other usage.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Tested-by: Frank Li <frank.li@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Tue, 22 Oct 2013 03:13:41 +0000 (11:13 +0800)]
usb: chipidea: host: more enhancement when ci->hcd is NULL
Like http://marc.info/?l=linux-usb&m=138200449428874&w=2 said:
two more things are needed to be done:
- If host_start fails, the host_stop should not be called, so we
add check that ci->hcd is not NULL.
- if the host_start fails at the beginning, we need to consider
regulator mismatch issue.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Takashi Iwai [Thu, 24 Oct 2013 12:25:32 +0000 (14:25 +0200)]
ALSA: Add ifdef CONFIG_GENERIC_ALLOCATOR for SNDRV_DMA_TYPE_IRAM code
It turned out that we can't use gen_pool_*() functions on archs
without CONFIG_GENERIC_ALLOCATOR (resulting in missing symbols), since
linux/genalloc.h doesn't provide dummy functions for all. We'd be
able to fix linux/genalloc.h size, but I take an easier path for
now...
usb/chipidea: fix oops on memory allocation failure
When CMA fails to initialize in v3.12-rc4, the chipidea driver oopses
the kernel while trying to remove and put the HCD which doesn't exist:
WARNING: CPU: 0 PID: 6 at /home/rmk/git/linux-rmk/arch/arm/mm/dma-mapping.c:511
__dma_alloc+0x200/0x240()
coherent pool not initialised!
Modules linked in:
CPU: 0 PID: 6 Comm: kworker/u2:0 Tainted: G W 3.12.0-rc4+ #56
Workqueue: deferwq deferred_probe_work_func
Backtrace:
[<c001218c>] (dump_backtrace+0x0/0x10c) from [<c0012328>] (show_stack+0x18/0x1c)
r6:c05fd9cc r5:000001ff r4:00000000 r3:df86ad00
[<c0012310>] (show_stack+0x0/0x1c) from [<c05f3a4c>] (dump_stack+0x70/0x8c)
[<c05f39dc>] (dump_stack+0x0/0x8c) from [<c00230a8>] (warn_slowpath_common+0x6c/0x8c)
r4:df883a60 r3:df86ad00
[<c002303c>] (warn_slowpath_common+0x0/0x8c) from [<c002316c>] (warn_slowpath_fmt+0x38/0x40)
r8:ffffffff r7:00001000 r6:c083b808 r5:00000000 r4:df2efe80
[<c0023134>] (warn_slowpath_fmt+0x0/0x40) from [<c00196bc>] (__dma_alloc+0x200/0x240)
r3:00000000 r2:c05fda00
[<c00194bc>] (__dma_alloc+0x0/0x240) from [<c001982c>] (arm_dma_alloc+0x88/0xa0)
[<c00197a4>] (arm_dma_alloc+0x0/0xa0) from [<c03e2904>] (ehci_setup+0x1f4/0x438)
[<c03e2710>] (ehci_setup+0x0/0x438) from [<c03cbd60>] (usb_add_hcd+0x18c/0x664)
[<c03cbbd4>] (usb_add_hcd+0x0/0x664) from [<c03e89f4>] (host_start+0xf0/0x180)
[<c03e8904>] (host_start+0x0/0x180) from [<c03e7c34>] (ci_hdrc_probe+0x360/0x670
)
r6:df2ef410 r5:00000000 r4:df2c3010 r3:c03e8904
[<c03e78d4>] (ci_hdrc_probe+0x0/0x670) from [<c0311044>] (platform_drv_probe+0x20/0x24)
[<c0311024>] (platform_drv_probe+0x0/0x24) from [<c030fcac>] (driver_probe_device+0x9c/0x234)
...
---[ end trace c88ccaf3969e8422 ]---
Unable to handle kernel NULL pointer dereference at virtual address 00000028
pgd = c0004000
[00000028] *pgd=00000000
Internal error: Oops: 17 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 6 Comm: kworker/u2:0 Tainted: G W 3.12.0-rc4+ #56
Workqueue: deferwq deferred_probe_work_func
task: df86ad00 ti: df882000 task.ti: df882000
PC is at usb_remove_hcd+0x10/0x150
LR is at host_stop+0x1c/0x3c
pc : [<c03cacec>] lr : [<c03e88e4>] psr: 60000013
sp : df883b50 ip : df883b78 fp : df883b74
r10: c11f4c54 r9 : c0836450 r8 : df30c400
r7 : fffffff4 r6 : df2ef410 r5 : 00000000 r4 : df2c3010
r3 : 00000000 r2 : 00000000 r1 : df86b0a0 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 2f29404a DAC: 00000015
Process kworker/u2:0 (pid: 6, stack limit = 0xdf882240)
Stack: (0xdf883b50 to 0xdf884000)
...
Backtrace:
[<c03cacdc>] (usb_remove_hcd+0x0/0x150) from [<c03e88e4>] (host_stop+0x1c/0x3c)
r6:df2ef410 r5:00000000 r4:df2c3010
[<c03e88c8>] (host_stop+0x0/0x3c) from [<c03e8aa0>] (ci_hdrc_host_destroy+0x1c/0x20)
r5:00000000 r4:df2c3010
[<c03e8a84>] (ci_hdrc_host_destroy+0x0/0x20) from [<c03e7c80>] (ci_hdrc_probe+0x3ac/0x670)
[<c03e78d4>] (ci_hdrc_probe+0x0/0x670) from [<c0311044>] (platform_drv_probe+0x20/0x24)
[<c0311024>] (platform_drv_probe+0x0/0x24) from [<c030fcac>] (driver_probe_device+0x9c/0x234)
[<c030fc10>] (driver_probe_device+0x0/0x234) from [<c030ff28>] (__device_attach+0x44/0x48)
...
---[ end trace c88ccaf3969e8423 ]---
Fix this so at least we can continue booting and get to a shell prompt.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Wed, 9 Oct 2013 06:39:52 +0000 (14:39 +0800)]
usb: chipidea: udc: Fix spinlock recursion during bus reset
After configuration, the host also possible sends bus reset
at any time, at such situation, it will trigger below spinlock
recursion dump. This commit unlocks the spinlock before calling
gadget's disconnect.
BUG: spinlock recursion on CPU#0, swapper/0/0
lock: 0xbf128014, .magic: dead4ead, .owner: swapper/0/0, .owner_cpu: 0
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-next-20130910+ #106
[<80014e20>] (unwind_backtrace+0x0/0xec) from [<80011a6c>] (show_stack+0x10/0x14)
[<80011a6c>] (show_stack+0x10/0x14) from [<805c143c>] (dump_stack+0x94/0xbc)
[<805c143c>] (dump_stack+0x94/0xbc) from [<80282cf8>] (do_raw_spin_lock+0x16c/0x18c)
[<80282cf8>] (do_raw_spin_lock+0x16c/0x18c) from [<805c77e0>] (_raw_spin_lock_irqsave+0x50/0x5c)
[<805c77e0>] (_raw_spin_lock_irqsave+0x50/0x5c) from [<803cff88>] (ep_disable+0x24/0x110)
[<803cff88>] (ep_disable+0x24/0x110) from [<7f015d50>] (gserial_disconnect+0xa0/0x15c [u_serial])
[<7f015d50>] (gserial_disconnect+0xa0/0x15c [u_serial]) from [<7f01c06c>] (acm_disable+0xc/0x30 [usb_f_acm])
[<7f01c06c>] (acm_disable+0xc/0x30 [usb_f_acm]) from [<7f001478>] (reset_config.isra.10+0x34/0x5c [libcomposite])
[<7f001478>] (reset_config.isra.10+0x34/0x5c [libcomposite]) from [<7f0014d4>] (composite_disconnect+0x34/0x5c [libcomposite])
[<7f0014d4>] (composite_disconnect+0x34/0x5c [libcomposite]) from [<803d1024>] (udc_irq+0x770/0xce4)
[<803d1024>] (udc_irq+0x770/0xce4) from [<803cdcc0>] (ci_irq+0x98/0x164)
[<803cdcc0>] (ci_irq+0x98/0x164) from [<8007edfc>] (handle_irq_event_percpu+0x50/0x17c)
[<8007edfc>] (handle_irq_event_percpu+0x50/0x17c) from [<8007ef64>] (handle_irq_event+0x3c/0x5c)
[<8007ef64>] (handle_irq_event+0x3c/0x5c) from [<80081e98>] (handle_fasteoi_irq+0x98/0x168)
[<80081e98>] (handle_fasteoi_irq+0x98/0x168) from [<8007e598>] (generic_handle_irq+0x28/0x3c)
[<8007e598>] (generic_handle_irq+0x28/0x3c) from [<8000edf4>] (handle_IRQ+0x4c/0xb4)
[<8000edf4>] (handle_IRQ+0x4c/0xb4) from [<800085bc>] (gic_handle_irq+0x28/0x5c)
[<800085bc>] (gic_handle_irq+0x28/0x5c) from [<800125c0>] (__irq_svc+0x40/0x54)
Exception stack(0x8083bf68 to 0x8083bfb0)
bf60: 81533b8000000000000962348001d7608088e12c00000000
bf80: 8083a0008083a0008084290c805cb414808428ac8083a000000000018083bfb0
bfa0: 8000f1388000f13c60000013ffffffff
[<800125c0>] (__irq_svc+0x40/0x54) from [<8000f13c>] (arch_cpu_idle+0x30/0x3c)
[<8000f13c>] (arch_cpu_idle+0x30/0x3c) from [<8005eb94>] (cpu_startup_entry+0xf4/0x148)
[<8005eb94>] (cpu_startup_entry+0xf4/0x148) from [<807f1a2c>] (start_kernel+0x2c4/0x318)
BUG: spinlock lockup suspected on CPU#0, swapper/0/0
lock: 0xbf128014, .magic: dead4ead, .owner: swapper/0/0, .owner_cpu: 0
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-next-20130910+ #106
[<80014e20>] (unwind_backtrace+0x0/0xec) from [<80011a6c>] (show_stack+0x10/0x14)
[<80011a6c>] (show_stack+0x10/0x14) from [<805c143c>] (dump_stack+0x94/0xbc)
[<805c143c>] (dump_stack+0x94/0xbc) from [<80282c94>] (do_raw_spin_lock+0x108/0x18c)
[<80282c94>] (do_raw_spin_lock+0x108/0x18c) from [<805c77e0>] (_raw_spin_lock_irqsave+0x50/0x5c)
[<805c77e0>] (_raw_spin_lock_irqsave+0x50/0x5c) from [<803cff88>] (ep_disable+0x24/0x110)
[<803cff88>] (ep_disable+0x24/0x110) from [<7f015d50>] (gserial_disconnect+0xa0/0x15c [u_serial])
[<7f015d50>] (gserial_disconnect+0xa0/0x15c [u_serial]) from [<7f01c06c>] (acm_disable+0xc/0x30 [usb_f_acm])
[<7f01c06c>] (acm_disable+0xc/0x30 [usb_f_acm]) from [<7f001478>] (reset_config.isra.10+0x34/0x5c [libcomposite])
[<7f001478>] (reset_config.isra.10+0x34/0x5c [libcomposite]) from [<7f0014d4>] (composite_disconnect+0x34/0x5c [libcomposite])
[<7f0014d4>] (composite_disconnect+0x34/0x5c [libcomposite]) from [<803d1024>] (udc_irq+0x770/0xce4)
[<803d1024>] (udc_irq+0x770/0xce4) from [<803cdcc0>] (ci_irq+0x98/0x164)
[<803cdcc0>] (ci_irq+0x98/0x164) from [<8007edfc>] (handle_irq_event_percpu+0x50/0x17c)
[<8007edfc>] (handle_irq_event_percpu+0x50/0x17c) from [<8007ef64>] (handle_irq_event+0x3c/0x5c)
[<8007ef64>] (handle_irq_event+0x3c/0x5c) from [<80081e98>] (handle_fasteoi_irq+0x98/0x168)
[<80081e98>] (handle_fasteoi_irq+0x98/0x168) from [<8007e598>] (generic_handle_irq+0x28/0x3c)
[<8007e598>] (generic_handle_irq+0x28/0x3c) from [<8000edf4>] (handle_IRQ+0x4c/0xb4)
[<8000edf4>] (handle_IRQ+0x4c/0xb4) from [<800085bc>] (gic_handle_irq+0x28/0x5c)
[<800085bc>] (gic_handle_irq+0x28/0x5c) from [<800125c0>] (__irq_svc+0x40/0x54)
Exception stack(0x8083bf68 to 0x8083bfb0)
bf60: 81533b8000000000000962348001d7608088e12c00000000
bf80: 8083a0008083a0008084290c805cb414808428ac8083a000000000018083bfb0
bfa0: 8000f1388000f13c60000013ffffffff
[<800125c0>] (__irq_svc+0x40/0x54) from [<8000f13c>] (arch_cpu_idle+0x30/0x3c)
[<8000f13c>] (arch_cpu_idle+0x30/0x3c) from [<8005eb94>] (cpu_startup_entry+0xf4/0x148)
[<8005eb94>] (cpu_startup_entry+0xf4/0x148) from [<807f1a2c>] (start_kernel+0x2c4/0x318)
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Mon, 9 Sep 2013 08:48:29 +0000 (16:48 +0800)]
usb: gadget: zero: Add flexible auto remote wakeup test method
In order to increase test coverage, we can change the interval between
two remote wakeups every time, and the interval can be any user defined
value. This change will no affect current behavior if the user does not
use two introduced module paramters.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Peter Chen [Tue, 24 Sep 2013 04:47:55 +0000 (12:47 +0800)]
usb: chipidea: add ci_hdrc_enter_lpm API
This API is used to let the PHY enter/leave low power mode.
Before the controller going to work(at probe/resume), it needs to let
the PHY leave low power mode.
After the controller stopping working(at remove/suspend), it needs to
let the PHY enter low power mode to save power consumption.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Tue, 17 Sep 2013 04:37:23 +0000 (12:37 +0800)]
usb: chipidea: imx: Add usb_phy_shutdown at probe's error path
If not, the PHY will be active even the controller is not in use.
We find this issue due to the PHY's clock refcount is not correct
due to -EPROBE_DEFER return after phy's init.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Tue, 17 Sep 2013 04:37:20 +0000 (12:37 +0800)]
usb: chipidea: udc: fix the oops after rmmod gadget
When we rmmod gadget, the ci->driver needs to be cleared.
Otherwise, when we plug in usb cable again, the driver will
consider gadget is there, and go to enumeration procedure,
but in fact, it was removed.
Peter Chen [Tue, 17 Sep 2013 04:37:19 +0000 (12:37 +0800)]
usb: chipidea: udc: Consolidate the call of disconnect
The udc-core will call gadget's driver->disconnect, so we should avoid
calling gadget's disconnect again at ci_udc_stop in case the gadget's
unbind free some structs which is still used at gadget's disconnect.
Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Peter Chen [Tue, 10 Sep 2013 07:34:39 +0000 (15:34 +0800)]
chipidea: udc: free pending TD at removal procedure
There is a pending TD which is not freed after request finishes,
we do this due to a controller bug. This TD needs to be freed when
the driver is removed. It prints below error message when unload
chipidea driver at current code:
"ci_hdrc ci_hdrc.0: dma_pool_destroy ci_hw_td, b0001000 busy"
It indicates the buffer at dma pool are still in use.
This commit will free the pending TD at driver's removal procedure,
it can fix the problem described above.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Anson Huang [Mon, 4 Nov 2013 20:23:51 +0000 (15:23 -0500)]
ENGR00286041 arm: imx: avoid warning message of speed grading check on i.MX6DL
i.MX6DL did NOT have 1.2GHz setpoint, no need to check speed
grading fuse for 1.2GHz opp, otherwise, there will be always
warning message of "failed to disable 1.2 GHz OPP" when system
boot up on i.MX6DL.
mtd: nand: add more comment for MTD_NANDFLASH/MTD_MLCNANDFLASH
In current code, the MTD_NANDFLASH is used to represent both the SLC and
MLC. It is confusing to us.
By adding an explicit comment about these two macros, this patch makes it
clear that:
MTD_NANDFLASH : stands for SLC NAND,
MTD_MLCNANDFLASH : stands for MLC NAND (including TLC).
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Huang Shijie [Fri, 17 May 2013 03:17:33 +0000 (11:17 +0800)]
mtd: add the ecc info for some full-id nand chips
Add the ecc info for TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2 and TC58NVG6D2.
From these chips' datasheets, we know that:
The TC58NVG2S0F and TC58NVG3S0F require 4bit ECC for per 512byte.
The TC58NVG5D2 and TC58NVG6D2 require 40bits ECC for per 1024byte.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This helper detects that whether the mtd's type is nand type.
Now, it's clear that the MTD_NANDFLASH stands for SLC nand only.
So use the mtd_type_is_nand() to replace the old check method
to do the nand type (include the SLC and MLC) check.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Akinobu Mita [Sat, 3 Aug 2013 09:52:08 +0000 (18:52 +0900)]
mtd: tests: rename sources in order to link a helper object
Each mtd test module have a single source whose name is the same as
the module name. In order to link a single object including helper
functions to every test module, this rename these sources to the
different names.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Vikram Narayanan <vikram186@gmail.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Thu, 2 May 2013 21:18:51 +0000 (14:18 -0700)]
mtd: tests: don't print error messages when out-of-memory
These strings are now unnecessary and discouraged in the kernel. The
kernel will have plenty of big scary messages if kmalloc fails. These
now only serve to bloat the module.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
The following are wrapper functions for mtd_read() and mtd_write()
which can simplify the return value check.
- mtdtest_read()
- mtdtest_write()
All helpers are put into a single .c file and it will be linked to
every test module later. The code will actually be copied to every
test module, but it is fine for our small test infrastructure.
[dwmw2: merge later 'return -EIO when mtdtest_read() failed' fix]
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Vikram Narayanan <vikram186@gmail.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Robin Gong [Fri, 1 Nov 2013 03:36:03 +0000 (11:36 +0800)]
ENGR00285897 mx6 busfreq: fix system crash while enter low bus with 'maxcpus=1'
Use for_each_online_cpu instead of for_each_present_cpu to take this case,
otherwise system will crash as below when go into low bus with 'maxcpus=1'
setting in command line.
Bug log during kernel boot:
...
failed to find fsl,imx6q-iomux-gpr regmap
...
The issue is imx6q_1588_init() is called before of_platform_populate().
of_platform_populate() walks the device tree and creates devices from
nodes. imx6q_1588_init() call syscon_regmap_lookup_by_compatible() to
get the device base on the given device node, since the device cannot
created for the node, so it is failed.
So, move the 1588 init function to behind of of_platform_populate().
Huang Shijie [Fri, 17 May 2013 03:17:27 +0000 (11:17 +0800)]
mtd: add data structures for Extended Parameter Page
Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
to store the ECC info.
The onfi spec tells us that if the nand chip's recommended ECC codeword
size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
read the Extended ECC information that is part of the extended parameter
page to retrieve the ECC requirements for this device.
This patch adds
[1] the neccessary fields for nand_onfi_params{},
[2] and adds the onfi_ext_ecc_info{} for Extended ECC information,
[3] adds onfi_ext_section{} for extended sections,
[4] and adds onfi_ext_param_page{} for the Extended Parameter Page.
Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
[Brian: amended for checkpatch.pl] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 16 Aug 2013 02:10:04 +0000 (10:10 +0800)]
mtd: add a new ecc_step_size field to mtd_info{}
In order to implement the NAND boot for some Freescale's chips, such as
imx23/imx28/imx50/imx6, we use a tool (called kobs-ng) to burn the uboot
and some metadata to nand chip. And the ROM code will use the metadata to
configrate the BCH, and to find the uboot.
The ECC information(ecc step size, ecc strength) which is used to configrure
the BCH is part of the metadata. The kobs-ng can get the ecc strength from
the sys node /sys/*/ecc_strength now. But it can not get the ecc step size.
This patch adds a new field to store the ecc step size in mtd_info{}, and
it makes preparation for the next patches.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Wed, 28 Aug 2013 01:45:10 +0000 (18:45 -0700)]
mtd: nand: hack ONFI for non-power-of-2 dimensions
Some bright specification writers decided to write this in the ONFI spec
(from ONFI 3.0, Section 3.1):
"The number of blocks and number of pages per block is not required to
be a power of two. In the case where one of these values is not a
power of two, the corresponding address shall be rounded to an
integral number of bits such that it addresses a range up to the
subsequent power of two value. The host shall not access upper
addresses in a range that is shown as not supported."
This breaks every assumption MTD makes about NAND block/chip-size
dimensions -- they *must* be a power of two!
And of course, an enterprising manufacturer has made use of this lovely
freedom. Exhibit A: Micron MT29F32G08CBADAWP
"- Plane size: 2 planes x 1064 blocks per plane
- Device size: 32Gb: 2128 blockss [sic]"
This quickly hits a BUG() in nand_base.c, since the extra dimensions
overflow so we think it's a second chip (on my single-chip setup):
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0x44 (Micron MT29F32G08CBADAWP), 4256MiB, page size: 8192, OOB size: 744
------------[ cut here ]------------
kernel BUG at drivers/mtd/nand/nand_base.c:203!
Internal error: Oops - BUG: 0 [#1] SMP ARM
[... trim ...]
[<c02cf3e4>] (nand_select_chip+0x18/0x2c) from [<c02d25c0>] (nand_do_read_ops+0x90/0x424)
[<c02d25c0>] (nand_do_read_ops+0x90/0x424) from [<c02d2dd8>] (nand_read+0x54/0x78)
[<c02d2dd8>] (nand_read+0x54/0x78) from [<c02ad2c8>] (mtd_read+0x84/0xbc)
[<c02ad2c8>] (mtd_read+0x84/0xbc) from [<c02d4b28>] (scan_read.clone.4+0x4c/0x64)
[<c02d4b28>] (scan_read.clone.4+0x4c/0x64) from [<c02d4c88>] (search_bbt+0x148/0x290)
[<c02d4c88>] (search_bbt+0x148/0x290) from [<c02d4ea4>] (nand_scan_bbt+0xd4/0x5c0)
[... trim ...]
---[ end trace 0c9363860d865ff2 ]---
So to fix this, just truncate these dimensions down to the greatest
power-of-2 dimension that is less than or equal to the specified
dimension.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Current code sets the mtd->type with MTD_NANDFLASH for both
SLC and MLC. So the jffs2 may supports the MLC nand, but in actually,
the jffs2 should not support the MLC.
This patch uses the nand_is_slc() to check the nand cell type,
and set the mtd->type with the right nand type.
After this patch, the jffs2 only supports the SLC nand.
The side-effect of this patch:
Before this patch, the ioctl(MEMGETINFO) can only return with the
MTD_NANDFLASH; but after this patch, the ioctl(MEMGETINFO) will
return with the MTD_NANDFLASH for SLC, and MTD_MLCNANDFLASH for MLC.
So the user applictions(such as mtd-utils) should also changes a little
for this.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Huang Shijie [Fri, 17 May 2013 03:17:31 +0000 (11:17 +0800)]
mtd: add ECC info for nand_flash_dev{}
Add an instance of an anonymous struct to store the ECC info for full id
nand chips.
@ecc.strength_ds: ECC correctability from the datasheet.
@ecc.step_ds: ECC size required by the @ecc.strength_ds,
These two fields are all from the datasheet.
Also add the necessary macros to make the code simple and clean.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 17 May 2013 03:17:25 +0000 (11:17 +0800)]
mtd: add datasheet's ECC information to nand_chip{}
1.) Why add the ECC information to the nand_chip{} ?
Each nand chip has its requirement for the ECC correctability, such as
"4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte".
This ECC info is very important to the nand controller, such as gpmi.
Take the Micron MT29F64G08CBABA for example, its geometry is
8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB.
If we do not provide the ECC info to the gpmi nand driver, it has to
calculate the ECC correctability itself. The gpmi driver will gets the 56bit
ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility.
The gpmi will quits in this case. But in actually, the gpmi can supports
this nand chip if it can get the right ECC info.
2.) about the new fields.
The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds.
The two fields should be set from the nand chip's datasheets.
For example:
"4bit ECC for each 512Byte" could be:
@ecc_strength_ds = 4, @ecc_step_ds = 512.
"40bit ECC for each 1024Byte" could be:
@ecc_strength_ds = 40, @ecc_step_ds = 1024.
3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}?
The @strength and @size in nand_ecc_ctrl{} is used by the nand controller
driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet.
Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Thu, 11 Apr 2013 08:34:59 +0000 (01:34 -0700)]
mtd: nand: reword nand_chip bad block interface comments
This remedies a few problems:
(1) The use of "the" vs. "a" is a little confusing, IMO.
(2) nand_chip.block_bad is used exclusively for checking the OOB bad
block markers of a NAND. Any BBT functionality is handled in
nand_bbt.c, so this description should differentiate itself from
nand_bbt.c.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
If the ONFI extended parameter page gives codeword_size == 0, the
extended ECC information is corrupt and should not be used. Currently,
we (correctly) avoid using the information, but we don't report the
error to the caller, so the caller doesn't know that we didn't
initialize ecc_strength_ds and ecc_step_ds. Now the caller can warn the
user that it does not have sufficient information.
This also removes the false and useless "ONFI extended param page
detected" debug message (it was printed even on the aforementioned
corruption, and for the success case, we don't really want a print).
Brian Norris [Tue, 13 Aug 2013 17:51:55 +0000 (10:51 -0700)]
mtd: nand: cleanup ONFI printed errors, warnings
The ONFI detection routine is too verbose in some cases and not verbose
enough in others. This patch refactors it to print only when there are
significant warnings/errors.
Probing in 16-bit mode:
It is unnecessary to print until after the READID (address 20h)
command. READID *has* to work properly in whatever bus width
configuration we are in, or else no identification mode works. So we
can silence some useless warnings on systems which come up in 16-bit
mode and do not even respond with an O-N-F-I string.
Valid parameter page:
Nobody needs to see this. Do we inform the user every time other
hardware responds properly? Instead, add an error message if *no*
uncorrupted parameter pages are found.
ONFI ECC:
Most drivers don't yet use the reported minimum ECC values, so it
shouldn't yet be a fatal condition if the extended parameter page is
incorrect. But we should at least give a warning for the corner cases
that we don't expect.
ONFI flash detected:
Nobody needs to see this. This is the expected case, that we detect
ONFI properly, or else it wasn't ONFI-compliant and is detected by
some other routine.
Dan Carpenter [Fri, 9 Aug 2013 09:49:05 +0000 (12:49 +0300)]
mtd: nand: silence some shift wrap warnings
There are static checkers which complain when we declare variables as
64 bit bitfields but only use the lower 32 bits because of shift
wrapping. In this case "len" is declared as u64 as opposed to unsigned
long or something which might be 32 bits.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Fri, 17 May 2013 03:17:30 +0000 (11:17 +0800)]
mtd: replace the hardcode with the onfi_feature()
The current code uses the hardcode to detect the 16-bit bus width.
Use the onfi_feature() to replace it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
[Brian: small fixup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Wed, 22 May 2013 02:28:27 +0000 (10:28 +0800)]
mtd: get the ECC info from the Extended Parameter Page
Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
to store the ECC info.
The onfi spec tells us that if the nand chip's recommended ECC codeword
size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
read the Extended ECC information that is part of the extended parameter
page to retrieve the ECC requirements for this device.
This patch implement the reading of the Extended Parameter Page, and parses
the sections for ECC type, and get the ECC info from the ECC section.
Tested this patch with Micron MT29F64G08CBABAWP.
Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Tue, 25 Jun 2013 20:17:59 +0000 (13:17 -0700)]
mtd: nand: detect OOB size for Toshiba 24nm raw SLC
Toshiba NAND datasheets have not been very forthcoming on OOB size
information; they do not provide any bitfields in the ID string for
spare area. In their 24nm technology flash, however, Toshiba migrated
their NAND to have 32 bytes spare per 512 bytes of page area (up from
the traditional 16 bytes), as they now require 8-bit ECC or higher.
I have discussed this issue directly with Toshiba representatives, and
they acknowledge this problem. They recommend detecting these flash
based on their technology node as follows:
For 24nm Toshiba SLC raw NAND (not BENAND -- Built-in Ecc NAND), there
are 32 bytes of spare area for every 512 bytes of in-band data area.
We can implement this rule with the following snippet of a device ID
decode table, which applies to all their 43nm, 32nm, and 24nm SLC NAND
(this table is not fully in the NAND datasheets, but it was provided
directly by Toshiba representatives):
Brian Norris [Sat, 10 Aug 2013 08:09:49 +0000 (01:09 -0700)]
mtd: nand: stop exporting nand_default_bbt
I removed the last non-nand_base users of this, and we shouldn't have
any more modules that need to access it. It's only non-static to share
between nand_base and nand_bbt.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:53:00 +0000 (17:53 -0700)]
mtd: nand: remove NAND_BBT_SCANEMPTY
NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.
NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.
nand_base.c shouldn't have to know the implementation details of
nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the
bit masking and shifting to isolate a BBT entry.
Instead, just move some of the BBT code into a new nand_markbad_bbt()
interface. This interface allows external users (i.e., nand_base) to
mark a single block as bad in the BBT. Then nand_bbt will take care of
modifying the in-memory BBT and updating the flash-based BBT (if
applicable).
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
/*
* Note that numblocks is 2 * (real numblocks) here, see i+=2
* below as it makes shifting and masking less painful
*/
I don't think it ever could have been "less painful" to have to shift an
extra bit (or 2, or 3) at various points in nand_bbt.c (and even
outside, since we leak our in-memory format). But now it is certainly
more painful, since we have nice macros and functions to retrieve the
relevant portions of the BBT.
This patch removes any points where the block number is
doubled/halved/otherwise-shifted, instead representing the block number
in its most natural form: as the actual block number.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:52:55 +0000 (17:52 -0700)]
mtd: nand: add accessors, macros for in-memory BBT
There is an abundance of magic numbers and complicated shifting/masking
logic in the in-memory BBT code which makes the code unnecessary complex
and hard to read.
This patch adds macros to represent the 00b, 01b, 10b, and 11b
memory-BBT magic numbers, as well as two accessor functions for reading
and marking the memory-BBT bitfield for a given block.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Tue, 27 Aug 2013 09:29:07 +0000 (17:29 +0800)]
mtd: gpmi: imx6: fix the wrong method for checking ready/busy
In the imx6, all the ready/busy pins are binding togeter.
So we should always check the ready/busy pin of the chip 0.
In the other word, when the CS1 is enabled, we should also check the
ready/busy of chip 0; if we check the ready/busy of chip 1,
we will get the wrong result.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
David Woodhouse [Fri, 25 Oct 2013 14:03:59 +0000 (15:03 +0100)]
mtd: gpmi: fix ECC regression
The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by
computing the ECC strength and ECC step size ourselves.
Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info")
makes the driver use the ECC info (ECC strength and ECC step size)
provided by the MTD code, and creates a different NAND ECC layout
for the BCH, and use the new ECC layout. This causes a regression:
We can not mount the ubifs which was created by the old NAND ECC layout.
This patch fixes this issue by reverting to the legacy ECC layout.
We will probably introduce a new device-tree property to indicate that
the new ECC layout can be used. For now though, for the imminent 3.12
release, we just unconditionally revert to the 3.11 behaviour.
This leaves a harmless cosmetic warning about an unused function. At
this point in the cycle I really don't care.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Fri, 16 Aug 2013 02:10:08 +0000 (10:10 +0800)]
mtd: gpmi: remove the nand_scan()
In order to make the nand_scan() work, the current code uses the hack code
to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and
re-init some the ECC info in the gpmi_pre_bbt_scan().
This code is really a little ugly.
The patch does following changes:
(1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan().
(2) Init all the necessary values in the gpmi_init_last()
before we call the nand_scan_tail().
(3) remove the code setting the ECC info, let the mtd layer to do the
real job.
(4) remove the gpmi_scan_bbt(). we do not need this function any more.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 17 May 2013 03:17:34 +0000 (11:17 +0800)]
mtd: gpmi: set the BCH's geometry with the ecc info
If the nand chip provides us the ECC info, we can use it firstly.
The set_geometry_by_ecc_info() will use the ECC info, and
calculate the parameters we need.
Rename the old code to legacy_set_geometry() which will takes effect
when there is no ECC info from the nand chip or we fails in the ECC info case.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Wed, 31 Jul 2013 00:52:58 +0000 (17:52 -0700)]
mtd: nand: refactor chip->block_markbad interface
The chip->block_markbad pointer should really only be responsible for
writing a bad block marker for new bad blocks. It should not take care
of BBT-related functionality, nor should it handle bookkeeping of bad
block stats.
This patch refactors the 3 users of the block_markbad interface (plus
the default nand_base implementation) so that the common code is kept in
nand_block_markbad_lowlevel(). It removes some inconsistencies between
the various implementations and should allow for more centralized
improvements in the future.
Because gpmi-nand no longer needs the nand_update_bbt() function, let's
stop exporting it as well.
Wolfram Sang [Wed, 10 Jul 2013 15:57:41 +0000 (16:57 +0100)]
mtd: gpmi-nand: don't use devm_pinctrl_get_select_default() in probe
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
projects / karo-tx-linux.git / log