Huacai Chen [Wed, 7 Oct 2015 06:07:59 +0000 (14:07 +0800)]
MIPS: Loongson: Cleanup CONFIG_LOONGSON_SUSPEND.
Now LOONGSON_CHIPCFG register definition doesn't depend on CPUFREQ any
more, so CPU_SUPPORTS_CPUFREQ is no longer needed for suspend/resume.
Remove CONFIG_LOONGSON_SUSPEND and use CONFIG_SUSPEND instead.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11274/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Wed, 4 Nov 2015 12:14:14 +0000 (13:14 +0100)]
MIPS: lantiq: Initialize the USB core on boot
There is a DWC2 USB core in these SoCs. To make USB work we need to first
reset and power the state machine. These are SoC specific registers and
not part of the actual USB core.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11449/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Wed, 4 Nov 2015 10:50:11 +0000 (11:50 +0100)]
MIPS: ralink: Remove check for CONFIG_PCI on non-PCI SoCs
The code currently panics if PCI is enabled but the SoC has no PCI bus.
This check is superfluous as the driver only loads if enabled in the
devicetree.
John Crispin [Thu, 5 Nov 2015 02:59:58 +0000 (03:59 +0100)]
MIPS: ralink: Add tty detection
MT7688 has several uarts that can be used for console. There are several
boards in the wild, that use ttyS1 or ttyS2. This patch applies a simply
autodetection routine to figure out which ttyS the bootloader used as
console. The uarts come up in 6 bit mode by default. The bootloader will
have set 8 bit mode on the console. Find that 8bit tty and use it.
John Crispin [Wed, 4 Nov 2015 10:50:08 +0000 (11:50 +0100)]
MIPS: ralink: Fix usb issue during frequency scaling
If the USB HCD is running and the cpu is scaled too low, then the USB
stops working. Increase the idle speed of the core to fix this if the
kernel is built with USB support.
The "magic" values are taken from the Ralink SDK Kernel.
Hauke Mehrtens [Wed, 28 Oct 2015 22:37:44 +0000 (23:37 +0100)]
MIPS: Lantiq: Fix check for return value of request_mem_region()
request_mem_region() returns a pointer and not an integer with an error
value. A check for "< 0" on a pointer will cause problems, replace it
with not null checks instead. This was found with sparse.
Hauke Mehrtens [Wed, 28 Oct 2015 22:37:35 +0000 (23:37 +0100)]
MIPS: Lantiq: Deactivate most of the devices by default
When the SoC starts up most of the devices should be deactivated by the
PMU, they should be activated when they get used by their drivers. Some
devices should not get deactivate at startup like the serial, register
them in a special way.
Hauke Mehrtens [Wed, 28 Oct 2015 22:37:30 +0000 (23:37 +0100)]
MIPS: Lantiq: Add locking for PMU register and check status afterwards
The PMU register are accessed in a non atomic way and they could be
accessed by different threads simultaneously, which could cause
problems this patch adds locking around the PMU registers. In
addition we now also wait till the PMU is actually deactivated.
[ralf@linux-mips.org: Fix spelling mistake in commit message as noticed
by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.]
Rafał Miłecki [Mon, 26 Oct 2015 10:13:16 +0000 (11:13 +0100)]
MIPS: BCM47xx: Fetch board info directly in callback function
This drops another symbol dependency between setup.c and sprom.c which
will allow us to make SPROM code a separated module (and share it with
ARM).
Patch tested on Linksys WRT300N V1.
Rafał Miłecki [Sun, 25 Oct 2015 21:16:47 +0000 (22:16 +0100)]
MIPS: BCM47xx: Support on-SoC bus in SPROM reading function
To support (extract) SPROM on Broadcom ARM devices we should separate
SPROM code and make it a separated module. We won't want to export
bcm47xx_fill_sprom symbol so we should support SoC SPROM in the standard
fallback function and then modify ssb to use it.
Hauke Mehrtens [Sun, 25 Oct 2015 22:21:42 +0000 (23:21 +0100)]
MIPS: lantiq: add clk_round_rate()
This adds a basic implementation of clk_round_rate()
The clk_round_rate() function is called by multiple drivers and
subsystems now and the lantiq clk driver is supposed to export this,
but doesn't do so, this causes linking problems like this one:
ERROR: "clk_round_rate" [drivers/media/v4l2-core/videodev.ko] undefined!
Julia Lawall [Sun, 25 Oct 2015 21:24:25 +0000 (22:24 +0100)]
MIPS: pci-rt3883: drop unneeded of_node_get
for_each_child_of_node performs an of_node_get on each iteration, so no
of_node_get is needed on breaking out of the loop when the device_node
structure is saved in another variable.
A simplified semantic match that finds this problem is as follows
(http://coccinelle.lip6.fr):
// <smpl>
@@
expression root;
local idexpression child;
@@
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Cc: kernel-janitors@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Cooper <jason@lakedaemon.net>
Patchwork: https://patchwork.linux-mips.org/patch/11357/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 21 Oct 2015 08:57:44 +0000 (09:57 +0100)]
MIPS: VDSO: Add implementations of gettimeofday() and clock_gettime()
Add user-mode implementations of gettimeofday() and clock_gettime() to
the VDSO. This is currently usable with 2 clocksources: the CP0 count
register, which is accessible to user-mode via RDHWR on R2 and later
cores, or the MIPS Global Interrupt Controller (GIC) timer, which
provides a "user-mode visible" section containing a mirror of its
counter registers. This section must be mapped into user memory, which
is done below the VDSO data page.
When a supported clocksource is not in use, the VDSO functions will
return -ENOSYS, which causes libc to fall back on the standard syscall
path.
When support for neither of these clocksources is compiled into the
kernel at all, the VDSO still provides clock_gettime(), as the coarse
realtime/monotonic clocks can still be implemented. However,
gettimeofday() is not provided in this case as nothing can be done
without a suitable clocksource. This causes the symbol lookup to fail
in libc and it will then always use the standard syscall path.
This patch includes a workaround for a bug in QEMU which results in
RDHWR on the CP0 count register always returning a constant (incorrect)
value. A fix for this has been submitted, and the workaround can be
removed after the fix has been in stable releases for a reasonable
amount of time.
A simple performance test which calls gettimeofday() 1000 times in a
loop and calculates the average execution time gives the following
results on a Malta + I6400 (running at 20MHz):
[markos.chandras@imgtec.com:
- Minor code re-arrangements in order for mappings to be made
in the order they appear to the process' address space.
- Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef
- Use gic_get_usm_range so we can do the GIC mapping in the
arch/mips/kernel/vdso instead of the GIC irqchip driver]
Signed-off-by: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Mon, 12 Oct 2015 09:40:43 +0000 (10:40 +0100)]
irqchip: irq-mips-gic: Provide function to map GIC user section
The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.
When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.
[markos.chandras@imgtec.com:
- Move mapping code to arch/mips/kernel/vdso.c and use a resource
type to get the GIC usermode information
- Avoid renaming function arguments and use __gic_base_addr to hold
the base GIC address prior to ioremap.]
[ralf@linux-mips.org: Fix up gic_get_usm_range() to compile and make inline
again.]
Signed-off-by: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/11281/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 21 Oct 2015 08:54:38 +0000 (09:54 +0100)]
MIPS: Initial implementation of a VDSO
Add an initial implementation of a proper (i.e. an ELF shared library)
VDSO. With this commit it does not export any symbols, it only replaces
the current signal return trampoline page. A later commit will add user
implementations of gettimeofday()/clock_gettime().
To support both new toolchains and old ones which don't generate ABI
flags section, we define its content manually and then use a tool
(genvdso) to patch up the section to have the correct name and type.
genvdso also extracts symbol offsets ({,rt_}sigreturn) needed by the
kernel, and generates a C file containing a "struct mips_vdso_image"
containing both the VDSO data and these offsets. This C file is
compiled into the kernel.
On 64-bit kernels we require a different VDSO for each supported ABI,
so we may build up to 3 different VDSOs. The VDSO to use is selected by
the mips_abi structure.
A kernel/user shared data page is created and mapped below the VDSO
image. This is currently empty, but will be used by the user time
function implementations which are added later.
[markos.chandras@imgtec.com:
- Add more comments
- Move abi detection in genvdso.h since it's the get_symbol function
that needs it.
- Add an R6 specific way to calculate the base address of VDSO in order
to avoid the branch instruction which affects performance.
- Do not patch .gnu.attributes since it's not needed for dynamic linking.
- Simplify Makefile a little bit.
- checkpatch fixes
- Restrict VDSO support for binutils < 2.25 for pre-R6
- Include atomic64.h for O32 variant on MIPS64]
Signed-off-by: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: mpc30x_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts mpc30x_defconfig to use libata PATA
drivers.
PS This platform still uses "ide0=base[,ctl[,irq]]" hack in
its defconfig. The hack itself has been removed in 2008 and
this platform should be converted to using PATA platform host
driver (pata_platform) instead.
MIPS: maltaup_xpa_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts maltaup_xpa_defconfig to use libata PATA
drivers (tc86c001 IDE host driver has no corresponding libata
driver yet so it is not converted).
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: maltaup_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts maltaup_defconfig to use libata PATA
drivers.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11142/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: maltasmvp_eva_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts maltasmvp_eva_defconfig to use libata PATA
drivers.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11139/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: maltaaprp_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts maltaaprp_defconfig to use libata PATA
drivers.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-ide@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: b.zolnierkie@samsung.com
Patchwork: https://patchwork.linux-mips.org/patch/11137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: malta_qemu_32r6_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts malta_qemu_32r6_defconfig to use libata
PATA drivers.
MIPS: malta_kvm_guest_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts malta_kvm_guest_defconfig to use libata
PATA drivers (tc86c001 IDE host driver has no corresponding
libata driver yet so it is not converted).
MIPS: malta_kvm_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts malta_kvm_defconfig to use libata PATA
drivers (tc86c001 IDE host driver has no corresponding libata
driver yet so it is not converted).
MIPS: malta_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts malta_defconfig to use libata PATA
drivers.
MIPS: lemote2f_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts lemote2f_defconfig to use libata PATA
drivers.
PS This platform uses CS5536 chipset which (due to historical
reasons) has basic support in AMD/nVidia PATA host driver and
full support in a newer CS5536 PATA one (pata_cs5536). Thus
most likely this platform should switch to using the latter
host driver.
MIPS: lasat_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts lasat_defconfig to use libata PATA
drivers.
MIPS: fuloong2e_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts fuloong2e_defconfig to use libata PATA
drivers.
MIPS: e55_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts e55_defconfig to use libata PATA drivers.
PS This platform still uses "ide0=base[,ctl[,irq]]" hack in
its defconfig. The hack itself has been removed in 2008 and
this platform should be converted to using PATA platform host
driver (pata_platform) instead.
MIPS: capcella_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts capcella_defconfig to use libata PATA
drivers.
MIPS: bigsur_defconfig: Convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority
(if not all) of Linux distributions have switched to use
libata for ATA support exclusively. However there are still
some users (mostly old or/and embedded non-x86 systems) that
have not converted from using IDE subsystem to libata PATA
drivers. This doesn't seem to be good thing in the long-term
for Linux as while there is less and less PATA systems left
in use:
* testing efforts are divided between two subsystems
* having duplicate drivers for same hardware confuses users
This patch converts bigsur_defconfig to use libata PATA
drivers (tc86c001 IDE host driver has no corresponding libata
driver yet so it is not converted).
Paul Burton [Tue, 22 Sep 2015 19:03:37 +0000 (12:03 -0700)]
MIPS: Extend hardware table walking support to MIPS64
Extend the existing support for Hardware Table Walking (HTW) to MIPS64
systems by supporting PMDs & setting the pointer size bit in PWSize,
then ceasing to blacklist HTW on MIPS64 systems.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:58:43 +0000 (11:58 -0700)]
MIPS: Malta: Register UP SMP ops if all else fails
If we fail to register any real SMP implementations, fall back to
registering the dummy UP implementation. Otherwise when we build an SMP
kernel & run it on a system where the SMP implementations fail to probe
(eg. QEMU) the kernel will perform a NULL dereference attempting to call
mp_ops->smp_setup() from plat_smp_setup().
Notably this fixes booting kernels with CPS SMP enabled on QEMU, which
doesn't currently implement the CM, CPC or GIC.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Rob Herring <robh@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11223/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:56:38 +0000 (11:56 -0700)]
MIPS: Malta: Setup RAM regions via DT
Move memory configuration to be performed via device tree for the Malta
board. This moves more Malta specific code to malta-dtshim.c, leaving
the rest of the mti-malta code a little more board-agnostic. This will
be useful to share more code between boards, with the device tree
providing the board specifics as intended.
Since we can't rely upon Malta boards running a bootloader capable of
handling devictrees & filling in the required information, a piece of
shim code (malta_dt_shim) is added to consume the (e)memsize variables
provided as part of the bootloader environment (or on the kernel command
line) then generate the DT memory node using the provided values.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Rob Herring <robh+dt@kernel.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Mark Rutland <mark.rutland@arm.com>
Patchwork: https://patchwork.linux-mips.org/patch/11222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:56:37 +0000 (11:56 -0700)]
MIPS: Malta: Remove fw_memblock_t abstraction
The fw_getmdesc function & fw_memblock_t abstraction is only used by
Malta, and so far as I can tell serves no purpose beyond making the code
less clear than it could be. Remove the useless level of abstraction.
Paul Burton [Tue, 22 Sep 2015 18:42:53 +0000 (11:42 -0700)]
MIPS: Allow RIXI for 32-bit kernels on MIPS64
Commit a68d09a156b2 ("MIPS: Don't use RI/XI with 32-bit kernels on
64-bit CPUs") prevented use of RIXI on MIPS64 systems, stating that the
"TLB handlers cannot handle this case". What they actually couldn't
handle was cases where there were less fill bits in the Entry{Lo,Hi}
registers than bits used by software in PTEs. The handlers can now deal
with this case, so enable RIXI for MIPS32 kernels on MIPS64 systems.
Note that beyond the obvious benefits provided by having RIXI on such
systems, this is required for systems implementing MIPSr6 where RIXI
cannot be disabled.
This reverts commit a68d09a156b2 ("MIPS: Don't use RI/XI with 32-bit
kernels on 64-bit CPUs").
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11219/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 748e787eb6de ("MIPS: Optimize TLB refill for RI/XI
configurations.") stopped explicitly clearing the bits used by software
in PTEs by making use of a rotate instruction that rotates them into the
fill bits of the Entry{Lo,Hi} register. This can only work if there are
actually enough fill bits in the register to cover the software
maintained bits, otherwise we end up writing those bits into the upper
bits of the PFN or PFNX field of the Entry{Lo,Hi} register.
Fix this by detecting the number of fill bits present in the
Entry{Lo,Hi} registers & explicitly clearing the software bits where
necessary.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:42:51 +0000 (11:42 -0700)]
MIPS: Tidy EntryLo bit definitions, add PFN
Tidy up the definition of the EntryLo RI & XI bits using BITS_PER_LONG
rather than #ifdef'ing on CONFIG_64BIT, and add a definition for the
offset to the PFN field for use by a later patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:42:50 +0000 (11:42 -0700)]
MIPS: tlbex: Share MIPS32 32 bit phys & MIPS64 64 bit phys code
The code in build_update_entries for 64 bit physical addresses on a
MIPS64 CPU and 32 bit physical addresses on a MIPS32 CPU is now
identical, with the exception of r4k bug workaround in the latter which
would simply not apply to the former. Remove the duplication and some
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:42:49 +0000 (11:42 -0700)]
MIPS: tlbex: Remove some RIXI redundancy
The cpu_has_rixi cases in build_update_entries are now identical to the
non-RIXI cases with the one exception of the r45k_bvahwbug case which is
hardcoded as never happening anyway & presumably was either missed from
the RIXI path or would never happen on a CPU with RIXI support. Remove
the redundant checks & duplication.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11215/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:24:20 +0000 (11:24 -0700)]
MIPS: Always use r4k_wait_irqoff for MIPSr6
Prior to release 6 of the MIPS architecture it has been implementation
dependent whether masked interrupts cause a wait instruction to return,
so the kernel has effectively had to maintain a whitelist of cores upon
which it is safe to use the r4k_wait_irqoff cpu_wait implementation.
With MIPSr6 this is no longer implementation dependent and
r4k_wait_irqoff can always be used.
Remove the existing I6400 case which will no longer ever be hit, and was
incorrect anyway since I6400 & r6 in general doesn't have the WII bit.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:12:18 +0000 (11:12 -0700)]
MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core
Ensure the update to which core the core-other GCR regions reflect has
taken place before any core-other GCRs are accessed by placing a memory
barrier (sync instruction) between the write to the core-other registers
and any such GCR accesses.
Paul Burton [Tue, 22 Sep 2015 18:12:17 +0000 (11:12 -0700)]
MIPS: CM: make use of mips_cm_{lock,unlock}_other
Document that CPC core-other accesses must take place within the bounds
of the CM lock, and begin using the CM lock functions where we access
the GCRs of other cores. This is required because with CM3 the CPC began
using GCR_CL_OTHER instead of CPC_CL_OTHER.
Paul Burton [Tue, 22 Sep 2015 18:12:16 +0000 (11:12 -0700)]
MIPS: CM: Introduce core-other locking functions
Introduce mips_cm_lock_other & mips_cm_unlock_other, mirroring the
existing CPC equivalents, in order to lock access from the current core
to another via the core-other GCR region. This hasn't been required in
the past but with CM3 the CPC starts using GCR_CL_OTHER rather than
CPC_CL_OTHER and this will be required for safety.
Paul Burton [Tue, 22 Sep 2015 18:12:15 +0000 (11:12 -0700)]
MIPS: CM: Fix GCR_Cx_CONFIG PVPE mask
The PVPE (or PVP in >= CM3) field is 10 bits wide, but the mask
previously only covered the bottom 9 bits. Extend the mask to cover all
10 bits of the field.
Paul Burton [Tue, 22 Sep 2015 18:12:14 +0000 (11:12 -0700)]
MIPS: CPS: Warn if a core doesn't start
When debugging core bringup it is useful to see the state of the CPC
sequencer, so output that value if the core hasn't started within a
reasonable amount of time (1 second). This avoids simply appearing to
the user to hang if a secondary core fails to start.
Paul Burton [Tue, 22 Sep 2015 18:12:13 +0000 (11:12 -0700)]
MIPS: CPS: Skip Config1 presence check
The Config1 register is architecturally defined as required, and is thus
present in all systems which may make use of cps-vec.S. Skip the check
for its presence via the Config.M bit.
Paul Burton [Tue, 22 Sep 2015 18:12:12 +0000 (11:12 -0700)]
MIPS: CPS: Read CM GCR base from cop0
Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register, converting from the physical address to an uncached
virtual address.
Paul Burton [Tue, 22 Sep 2015 18:12:11 +0000 (11:12 -0700)]
MIPS: CPS: Early debug using an ns16550-compatible UART
Provide support for outputting early debug information, in the form of
various register values should an exception occur, during the early
bringup of secondary cores. This code requires an ns16550-compatible
UART accessible from the secondary core, and is written in assembly due
to the environment in which such early exceptions occur where way may
not have a stack, be coherent or even have initialised caches.
[ralf@linux-mips.org: Fix merge conflict.]
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11202/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
James Hogan [Tue, 10 Nov 2015 17:06:37 +0000 (17:06 +0000)]
MIPS: Fix duplicate CP0_* definitions.
Remove the definition in locore.S and move a few of the other similar
definitions in asm/mipsregs.h too. CP0_INTCTL, CP0_SRSCTL, & CP0_SRSMAP
are unused so they're just dropped instead. CP0_DDATA_LO is left where
it is as I have patches to eliminate its use in locore.S and it
otherwise is unlikely to need to be used from assembly code.
Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 18:12:10 +0000 (11:12 -0700)]
MIPS: CPS: Set Status.KX on entry for MIPS64 kernels
If the kernel may make use of 64 bit addresses outside of the
compatibility address space then we need to set KX such that those
accesses can succeed. Do so for MIPS64 kernels.
Paul Burton [Tue, 22 Sep 2015 18:12:09 +0000 (11:12 -0700)]
MIPS: CPS: Set Status.BEV bit during early boot
Set the Status.BEV bit throughout the early startup of a secondary core
such that if an exception occurs the core branches to one of the
exception vector entries from cps-vec.S, rather than branching to
whatever is set in EBase.
Paul Burton [Tue, 22 Sep 2015 17:26:41 +0000 (10:26 -0700)]
MIPS: Always read full 64 bit CM error GCRs for CM3
CM3 has 64 bit GCR_ERROR_* registers, but the code in
mips_cm_error_report was previously only reading 32 bits of it in MIPS32
kernels. Fix by splitting the reads for CM2 & CM3, and making use of the
read64_ variants of the accessor function for CM3.
Paul Burton [Tue, 22 Sep 2015 17:26:40 +0000 (10:26 -0700)]
MIPS: Allow read64 GCR accessors to work on MIPS32 kernels
If we run a MIPS32 kernel on a system using CM3 we may still need to
access 64 bit GCRs, as will be done in later patches. Allow this by
having the read64_gcr_* accessor functions perform 2 x 32 bit reads on
those systems.
Paul Burton [Tue, 22 Sep 2015 17:26:39 +0000 (10:26 -0700)]
MIPS: Avoid buffer overrun in mips_cm_error_report
Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache
errors") added cases for decoding errors reported by CM3, but leaves the
buf variable which is printed as a string uninitialised for cause values
other than 1, 2 or 3. Fix by ensuring the buf variable is initialised to
an empty string in such cases.
Paul Burton [Tue, 22 Sep 2015 17:26:38 +0000 (10:26 -0700)]
MIPS: Don't read GCRs when a CM is not present
Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache
errors") leads to Malta boards unconditionally reading CM GCRs upon bus
errors, regardless of whether a CM is present. This is incorrect & will
lead to further exceptions. Fix by moving the GCR reads to after the
check for whether a CM is present.
Paul Burton [Tue, 22 Sep 2015 17:26:37 +0000 (10:26 -0700)]
MIPS: Clarify mips_cm_is64 documentation
The documentation for mips_cm_is64 implied that the width of the CM GCRs
would change depending upon the CPU, which is not true. Reword the
explanation to be clearer that the GCR width is purely dependent upon
the version of the CM.
Paul Burton [Tue, 22 Sep 2015 17:16:39 +0000 (10:16 -0700)]
MIPS: Allow 24Hz timer frequency
A boundary exists beyond which the timer frequency becomes high enough
that timer interrupts saturate the system and either cause it to slow to
a crawl or stop functioning entirely. Where that boundary lies depends
upon a number of factors such as the overhead of each interrupt and the
overall speed of the CPU, but correlates strongly with the clock
frequency at which the CPU runs. When running on emulators during
bringup or debug of a CPU that clock frequency is very low, which
results in the boundary at which the timer frequency becomes
unsustainable being very low. The current minimum of 48Hz pushes against
boundary in certain situations in current systems. Allow the kernel to
be configured for a 24Hz timer frequency in order to avoid problems on
such slow running systems.
Paul Burton [Tue, 22 Sep 2015 17:15:22 +0000 (10:15 -0700)]
MIPS: traps: tidy up ebase calculation
Rather than #ifdef on CONFIG_KVM_GUEST & redefine the guest kseg0 base
locally, make use of the CAC_BASE macro which has the correct value in
both cases.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Thierry Reding [Mon, 5 Oct 2015 11:31:17 +0000 (13:31 +0200)]
MIPS: JZ4740: Use PWM lookup table
Associate the PWM with the pwm-beeper device using a PWM lookup table.
This will eventually allow the legacy function calls to pwm_request() to
be removed from all consumer drivers.
ARCH_USE_BUILTIN_BSWAP will use __builtin_bswap16(), __builtin_bswap32()
and __builtin_bswap64() where available. This allows better instruction
scheduling. On pre-R2 processors it will result in 32 bit and 64 bit
swapping being performed in a call to a __bswapsi2() rsp. __bswapdi2()
functions, so we add these, too.
For a 4.2 kernel with GCC 4.9 this yields the following kernel sizes:
Presumably the code size improvments yield better cache hit rate thus
better performance compensating for the extra function call but this
will still need to be benchmarked.
Paul Burton [Tue, 22 Sep 2015 17:10:56 +0000 (10:10 -0700)]
MIPS: Allow L2 prefetch to be configured via debugfs
When debugging or examining the performance of a system it can be useful
to examine the effect of L2 prefetching. Provide an optional debugfs
entry to allow a user to enable or disable L2 prefetching.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11182/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 17:10:55 +0000 (10:10 -0700)]
MIPS: Declare mips_debugfs_dir in a header
We have many extern declarations of mips_debugfs_dir through arch/mips/
in various C files. Unify them by declaring mips_debugfs_dir in a
header, including it in each affected C file & removing the duplicate
declarations.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Joe Perches <joe@perches.com> Cc: Jaedon Shin <jaedon.shin@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: James Cowgill <James.Cowgill@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11181/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 17:10:54 +0000 (10:10 -0700)]
MIPS: Enable L2 prefetching for CM >= 2.5
On systems with CM 2.5 & beyond there may be L2 prefetch units present
which are not enabled by default. Detect them, configuring & enabling
prefetching when available.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 22 Sep 2015 17:10:53 +0000 (10:10 -0700)]
MIPS: Introduce API for enabling & disabling L2 prefetch
Introduce new functions in struct bcache_ops to enable & disable L2
cache prefetching, and to retrieve the current state of L2 prefetching.
This will be used in later patches.
Paul Burton [Tue, 22 Sep 2015 17:07:41 +0000 (10:07 -0700)]
MIPS: Allow compact branch policy to be changed
When debugging it can be helpful to change the policy for compiler use
of MIPSr6 compact branches, in order to rule out or home in on their
involvement in bugs. Allow the GCC -mcompact-branches= flag to be set
via Kconfig under the "Kernel hacking" menu.
Andrzej Hajda [Mon, 21 Sep 2015 13:34:08 +0000 (15:34 +0200)]
MIPS: Remove invalid check
Unsigned values cannot be lesser than zero.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
[ralf@linux-mips.org: Chris Dearman's original commit 9318c51acd9689505850152cc98277a6d6f2d752 ([MIPS] MIPS32/MIPS64 secondary
cache management) introduced these less than zero checks in 2.6.18.]
projects / karo-tx-linux.git / log