Tony Lin [Fri, 15 Jul 2011 02:59:38 +0000 (10:59 +0800)]
ENGR00153160 fix card interrupt issue on uSDHC and eSDHC
uSDHC: card interrupt storm if we do not clear card interrupt
status by sw.
eSDHC: card interrupt will be lost if we do not set D3CD bit.
apply the workarounds in sdhci-esdhc-imx.c to avoid adding new
QUIRKs.
Mx6 not works when connnect to a 1G switch.
This is caused by phy_dev->supported != PHY_GBIT_FEATURES, more bits
will set to phy_dev->supported when negotiation complete.
Terry Lv [Tue, 21 Jun 2011 06:29:52 +0000 (14:29 +0800)]
ENGR00139235-3: IIM(OCOPT): Enable IIM driver for iMX6Q
Add a new driver for On-Chip OTP controller. The driver
will register all the register names of all the banks to /sys/.
You can use the following commands to manipulate the OTP banks:
Tony Lin [Tue, 12 Jul 2011 03:09:29 +0000 (11:09 +0800)]
ENGR00152547-04 [MX6Q]add SDHC3.0 support on uSDHC controller
modify host controller driver to meet SD3.0 spec.
including voltage switch, and tuning control.
add a function pointer for bus driver to do tuning preparation,
in case some host controller like uSDHC does not tune automatically.
it needs change delay line before tuning.
Tony Lin [Tue, 12 Jul 2011 03:08:57 +0000 (11:08 +0800)]
ENGR00152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller
add voltage switch function due to SDHC3.0 spec requirement
add tuning function due to SDHC3.0 spec requirement
extend some functions to support SDR50 & SDR104 speed mode
Tony Lin [Tue, 12 Jul 2011 03:04:35 +0000 (11:04 +0800)]
ENGR00152547-01 [MX6Q]add SDHC3.0 support on uSDHC controller
enable uSDHC slot 3 in board file
add parameter in platform data to indicate whether the slot
supports 1.8 voltage
add pinmux to support voltage switch between 1.8V and 3.3V
Jason Chen [Wed, 13 Jul 2011 04:02:43 +0000 (12:02 +0800)]
ENGR00152845-1 MSL plat-mxc: ipuv3 display support in imx6q
1. work for multiple ipu instance
2. add mxc_dispdrv support
A display device driver could call mxc_dispdrv_register(drv) in its
dev_probe() function.
- Move all dev_probe() things into mxc_dispdrv_driver->init(), init()
function should init and feedback setting;
- Move all dev_remove() things into mxc_dispdrv_driver->deinit();
- Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
- Move all dev_resume() things into fb_notifier for RESUME, if there is;
ipuv3 fb driver would call mxc_dispdrv_init(drv_name, setting) before a
fb need be added, with fbi param passing by setting, after mxc_dispdrv_init()
return, FB driver should get the basic setting about fbi info and ipuv3-hw
(ipu_id and disp_id).
there are many display interfaces on imx5x or imx6x platform, all of them
are connected with ipuv3-DI, mxc_dispdrv can register display device as:
"lcd" -- display extend port for lcdif
"ldb" -- lvds bridge on chip (imx5x or imx6x)
"tve" -- tve for tveout on chip (imx5x)
"vga" -- vga through tve on chip (imx5x)
"hdmi" -- hdmi on platform with ddc support
(sii902x on imx53 - not enable yet)
hdmi on chip with ddc support
(imx6x - not enable yet)
"dvi" -- dvi port with ddc support (not enable yet)
take tvout as example, a dispdrv structure and register flow could like below:
"mxcfb0" means setting for fb0 device, ipuv3 fb driver will request setting
from registered dispdrv, these setting include what's the ipu and what's the
DI number this dev used. Normally, if one IPU is first used, ipuv3 fb driver
will create one overlay fb right after current fb driver create.
Take above cmdline as an example,
/dev/fb0 will be first fb device on 800x480 lcd.
/dev/fb1 will be overlay fb device on 800x480 lcd.
/dev/fb2 will be second fb device on VGA-XGA vga.
"dev=" means which display device(lcd,ldb,vga etc) you want choose for this fb.
"800x480M@55 or VGA-XGA" means the mode_str of video mode you want.
"if=" means the display device hw interface format.
such setting could be passed by platform data as a default value, cmdline
option will replace these values if there are.
3. modify ldb/tve driver and add mxc_lcdif driver.
For ldb driver, there are below modes could be set by cmdline options:
"ldb=spl0/1" -- split mode on DI0/1
"ldb=dul0/1" -- dual mode on DI0/1
"ldb=sin0/1" -- single mode on DI0/1
"ldb=sep" -- separate mode
there are two LVDS channels(LVDS0 and LVDS1) which can transfer video datas,
there two channels can be used as split/dual/single/separate mode.
split mode means display data from DI0 or DI1 will send to both channels
LVDS0+LVDS1.
dual mode means display data from DI0 or DI1 will be duplicated on LVDS0 and
LVDS1, it said, LVDS0 and LVDS1 has the same content.
single mode means only work for DI0->LVDS0 or DI1->LVDS1.
separate mode means you can make DI0->LVDS0 and DI1->LVDS1 work at the same
time.
Signed-off-by: Jason Chen <jason.chen@freescale.com>
Peter Chen [Mon, 11 Jul 2011 10:24:50 +0000 (18:24 +0800)]
ENGR00152915-1 mx6q-usb: refine usb phy usage
(Fixed the bug that PLL7 lock failed after usb enters low power mode)
After confirming with IC guys, the phy clock should be used
like below:
- OTG phy clock
EN_USB_CLKS: should be also enabled
PLL3 power: Enable/Disable on the fly
- Host1 phy clock
EN_USB_CLKS and PLL7 power should be also enabled at the initialization
PLL7 power will be totally controller by IC
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Fri, 8 Jul 2011 00:49:53 +0000 (08:49 +0800)]
ENGR00152842 mx5x-usb: fix build error
As well as some warnings for compiling
Fix the build error reported by Alan Tull, the error message is:
arch/arm/mach-mx5/usb_dr.c: In function 'mx5_usb_dr_init':
arch/arm/mach-mx5/usb_dr.c:309: error: implicit
declaration of function 'machine_is_mx53_loco'
The below warning message output when compiling mx5x kenrel:
arch/arm/plat-mxc/include/mach/arc_otg.h:36:7:
warning: "CONFIG_ARCH_MX6" is not defined
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Danny Nold [Tue, 5 Jul 2011 19:26:49 +0000 (14:26 -0500)]
ENGR00152681 - EPDC fb: Updates may be shifted right by 1 column
- Fixed PxP input left coordinate value. Was previously being incorrectly
computed such that the value would be incorrect when using 16bpp RGB and an
X coordinate that is offset from 4-pixel alignment by 1 (e.g. x=1, x=5).
The resulting effect was that updates meeting this criteria would be
drawn to the EPD panel shifted to the right by 1 pixel.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Peter Chen [Mon, 4 Jul 2011 07:58:39 +0000 (15:58 +0800)]
ENGR00152493-1 mx6q: add usb function
Changes at MSL
- Add usb code for mx6q
- Usb host functions (keyboard and u-disk) are verified
- USB host low power mode and wakeup are supported
- defconfig for otg port is for host port
- Using upstream platform device register method
- Delete some useless code, and fix the warning during building
Signed-off-by: Peter Chen <peter.chen@freescale.com>
ENGR00152528-1 MX6Q, ENET: add enet support for mx6q
Add enet driver support for mx6q sabreauto board.
Since ENET reset lost it mac address, we have to generate
mac address in random.
The prefer way to set mac address is pass from kernel command line
by "fec_mac=${ethaddr}" for sabreauto.
Currently only support basic temperature reading,
after the tester write the calibration value into
fuse, we will need to improve the accuracy of this
thermal sensor, also, the cooling device will be
added later.
Currently only support temperature reading, and
since the chip need calibration, and they will
write the calibration parameter into fuse later,
we need to wait for it and improve this thermal
sensor's accuracy. Also, cooling device will be
added later.
ENGR00151891: MX50-Fix bug in exit from LPAPM mode.
When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Zeng Zhaoming [Tue, 28 Jun 2011 02:23:16 +0000 (10:23 +0800)]
ENGR00139229-2 MX6: Bring up i.MX6 sabreauto with Quad cores
MSL code for bring up MX6 sabreauto board with Quad core.
Enable cpu core local timer, add reset and enable cpu core control,
and enable it in default config.
Merged from testbuild:imx6_bringup branch.
Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com>
- With FB_POWERDOWN_DISABLE is set as the powerdown delay (disabling the EPDC
driver from powering down), the EPDC driver was having problems going into
suspend. Any request to blank the EPDC driver would result in a timeout
and an error status. And subsequent attempts to send updates to the driver
would fail, as the driver's power state was incorrect. This patch prompts
the EPDC driver to be disabled when the blanking state is changed to
FB_BLANK_POWERDOWN and FB_POWERDOWN_DISABLE is set. Resultingly, the correct
driver power state is maintained and suspend/resume works correctly.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 21 Jun 2011 02:51:03 +0000 (21:51 -0500)]
ENGR00151822 - EPDC fb: Prevent endless collision by managing FULL mode updates
When using SNAPSHOT update scheme, submitting FULL mode updates can easily
lead to an endlessly looping sequence of collisions if any updates are active
when the new FULL mode update is submitted. Thus, we must first flush any
updates out before submitting a new FULL mode update.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Sammy He [Tue, 21 Jun 2011 16:08:22 +0000 (00:08 +0800)]
ENGR00151762 vpu: Fix system hang due to long time video playback on mx51
Fix system hang due to long time video playback. This issue is only
on i.MX51 platfrom due to changing vpu clock parent in vpu_enable/
disable. Set vpu clock parent to axi_a forever to fix it.
Danny Nold [Wed, 15 Jun 2011 14:11:51 +0000 (09:11 -0500)]
ENGR00151639 - EPDC fb: Memory for PxP workaround buffers may be reduced
- This patch changes the way that buffers are allocated and used for the
case where PxP alignment limitations are not met (a copy from the
update source buffer into a temporary buffer before initiating the
PxP processing task is required). Previously, a buffer was allocated
on a per-update basis, resulting in a large number of copy buffers. Now,
we allocate just one copy buffer that can be reused any time the PxP
alignment workaround is required. This is okay because it is assured
that only one PxP transaction can be prepared at a time.
Signed-off-by: Danny Nold <dannynold@freescale.com>
- When the powerdown delay is set to FB_POWERDOWN_DISABLE, the
mxc_epdc_fb_flush_updates() function does not execute correctly, always
resulting in a time out while waiting to receive a completion that signals
that all updates have completed. This causes long delays when changing the FB
mode, since a mode change will always result in a call to
mxc_epdc_fb_flush_updates().
Fixed this bug by creating a new mxc_epdc_fb_data variable to track whether
all active updates have completed. mxc_epdc_fb_flush_updates() now
keys off of this variable to determine whether to wait for all
active updates to complete.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 31 May 2011 21:23:48 +0000 (16:23 -0500)]
ENGR00144358 - EPDC fb: Fix race condition in how EPDC status is captured in IST
- Capture EPDC status registers up front in IST, rather than when-needed
during IST, to prevent potential race conditions where the status changes
mid-IST.
Signed-off-by: Danny Nold <dannynold@freescale.com>
- When synching update submission to EPDC end of frame (when tce_prevent is
defined), we should wait using wait_for_completion_timeout to prevent
hang/deadlock in case we don't receive completion.
- Added call in IST to disable end of frame interrupt upon receiving the
interrupt.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Sammy He [Tue, 31 May 2011 09:49:24 +0000 (17:49 +0800)]
ENGR00144306-2 vpu: Add iram info to vpu platform data for each platform
Add iram info to vpu platform data for each platform in linux/arch folder.
Disable iram on MX51 and enable iram on MX53 platform.
And remove VPU_IRAM_SIZE usage.
Sammy He [Tue, 31 May 2011 09:48:12 +0000 (17:48 +0800)]
ENGR00144306-1 VPU: remove VPU IRAM config and add iram info to plat data.
One kernel image is requested, however, we need to enable iram
for performance improvement on mx53, and disable it on mx51 due
to known issue. So use platform data to pass vpu iram disable/enable
flag. And considering requested iram size also can be different per
requirement, iram size is also set in platform data.
Liu Ying [Tue, 24 May 2011 02:06:03 +0000 (10:06 +0800)]
ENGR00142551-3 MXC V4L2:Change IPU interface for triple buffer
This patch changes IPU interface for MXC V4L2 to align with
IPUv3 triple buffer support.
When V4L2 is used, we'll change to use double buffer for
display channel via internal framebuffer interface.
Liu Ying [Tue, 24 May 2011 02:04:02 +0000 (10:04 +0800)]
ENGR00142551-2 IPUv3 FB:Support HW triple buffer
This patch supports HW triple buffer for IPUv3
framebuffer.
1) Remove buf ready check in EOF irq handler, as we
think the swap logic will not fail for HW triple
buffer case.
2) When V4L2 output/overlay are used, switch to double
buffer mode.
3) Changes IPU interface for IPUv1 framebuffer to pass
building.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit 4ada3031e13207902f8c90b33c082759889cb22a)
Liu Ying [Tue, 24 May 2011 01:58:49 +0000 (09:58 +0800)]
ENGR00142551-1 IPUv3:Support triple buffer
This patch supports IPUv3 triple buffer.
Only channel 23, 27 and 28 are tested.
Test was done on MX51 BBG and MX53 SMD.
IPUv1 interface is changed accordingly
to pass building.
Liu Ying [Tue, 24 May 2011 01:57:46 +0000 (09:57 +0800)]
ENGR00143575 IPUv3:Align IDMAC BS with DMFC FIFO BS
This patch aligns IDMAC burst size and DMFC FIFO burst
size to get better performance and workarounds black
flash issue when playing video on DP-FG with full
screen mode at 1024x768M@60.
Anish Trivedi [Fri, 20 May 2011 16:51:01 +0000 (11:51 -0500)]
ENGR00143799 Add SCC RAM clock to dependency list for SAHARA clock tree
When ARM is in WAIT mode, the SCC RAM clock is disabled since
1 is written to the CCGR register by default. At that point, if SAHARA
tries to access a key or some other piece of data stored in the SCC RAM,
then it might hang.
To prevent this scenario, SCC RAM is added to dependency list
for SCC clock, and SCC clock is added to dependency list for SAHARA.
Yuxi Sun [Wed, 18 May 2011 06:02:45 +0000 (14:02 +0800)]
ENGR00143550 camera: change camera platform data name and remove unused function
Change camera platform data name from mxc_camera_platform_data to
fsl_mxc_camera_platform_data in accordence with include/linux/fsl_devices.h
and remove unused function gpio_sensor_active(),gpio_sensor_inactive().
- Removed __initdata from regulator_init_data structure declaration. This
protects the MAX17135 regulator from having its structure overwritten, which
was causing a bug when writing large chunks of memory.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Liu Ying [Thu, 12 May 2011 12:18:25 +0000 (20:18 +0800)]
ENGR00143309 IPUv3fb:Set default yres_virtual to be 3*yres
This patch sets framebuffer yres_virtual to be 3*yres defaultly.
Before this patch is applied, the yres_virtual will be changed
to yres when hdmi cable is hot plugged out and in, which
reduces yres_virtual to yres and pan display mechanism cannot
work well.
In set_voltage function, all voltages are not in microvolts.
Hence set_voltage function was failing. Change all voltages in
the function to be in microvolts.
Liu Ying [Thu, 12 May 2011 09:59:34 +0000 (17:59 +0800)]
ENGR00142683 IPUv3:Increase IDMAC BS for RGBP and DMFC BS
This patch increases IDMAC burst size from 16 pixels to
32 pixels for RGBP pixel format and increases DMFC burst
size to 128 pixels to workaround 1080P60 display video
black flash issue.
projects / karo-tx-linux.git / log